ManuelW/grbl-LPC-CoreXY
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limit pins

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This commit is contained in:
Todd Fleming 2017-01-04 20:48:59 -05:00
parent bbbdb60076
commit fb5ba4cfb9
4 changed files with 19 additions and 23 deletions
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28
grbl/config.h
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@ -324,9 +324,9 @@
// normal-open switch and vice versa. // normal-open switch and vice versa.
// NOTE: All pins associated with the feature are disabled, i.e. XYZ limit pins, not individual axes. // NOTE: All pins associated with the feature are disabled, i.e. XYZ limit pins, not individual axes.
// WARNING: When the pull-ups are disabled, this requires additional wiring with pull-down resistors! // WARNING: When the pull-ups are disabled, this requires additional wiring with pull-down resistors!
//#define DISABLE_LIMIT_PIN_PULL_UP //#define DISABLE_LIMIT_PIN_PULL_UP Don't use; pull-up control not ported to ARM yet. pull-up is always on.
//#define DISABLE_PROBE_PIN_PULL_UP //#define DISABLE_PROBE_PIN_PULL_UP Don't use; pull-up control not ported to ARM yet. pull-up is always on.
//#define DISABLE_CONTROL_PIN_PULL_UP //#define DISABLE_CONTROL_PIN_PULL_UP Don't use; pull-up control not ported to ARM yet. pull-up is always on.
// Sets which axis the tool length offset is applied. Assumes the spindle is always parallel with // Sets which axis the tool length offset is applied. Assumes the spindle is always parallel with
// the selected axis with the tool oriented toward the negative direction. In other words, a positive // the selected axis with the tool oriented toward the negative direction. In other words, a positive
@ -610,20 +610,16 @@
// Define homing/hard limit switch input pins and limit interrupt vectors. // Define homing/hard limit switch input pins and limit interrupt vectors.
// NOTE: All limit bit pins must be on the same port, but not on a port with other input pins (CONTROL). // NOTE: All limit bit pins must be on the same port, but not on a port with other input pins (CONTROL).
#define LIMIT_DDR DDRB #define LIMIT_DDR LPC_GPIO0->FIODIR
#define LIMIT_PIN PINB #define LIMIT_PIN LPC_GPIO0->FIOPIN
#define LIMIT_PORT PORTB #define LIMIT_PORT LPC_GPIO0->FIOPIN
#define X_LIMIT_BIT 1 // Uno Digital Pin 9 #define X_LIMIT_BIT 25 // X-MIN=24, X-MAX=25
#define Y_LIMIT_BIT 2 // Uno Digital Pin 10 #define Y_LIMIT_BIT 27 // Y-MIN=26, Y-MAX=27
#ifdef VARIABLE_SPINDLE // Z Limit pin and spindle enabled swapped to access hardware PWM on Pin 11. #define Z_LIMIT_BIT 29 // Z-MIN=28, Z-MAX=29
#define Z_LIMIT_BIT 4 // Uno Digital Pin 12
#else
#define Z_LIMIT_BIT 3 // Uno Digital Pin 11
#endif
#define LIMIT_MASK ((1<<X_LIMIT_BIT)|(1<<Y_LIMIT_BIT)|(1<<Z_LIMIT_BIT)) // All limit bits #define LIMIT_MASK ((1<<X_LIMIT_BIT)|(1<<Y_LIMIT_BIT)|(1<<Z_LIMIT_BIT)) // All limit bits
#define LIMIT_INT PCIE0 // Pin change interrupt enable pin // hard/soft limit not ported #define LIMIT_INT PCIE0 // Pin change interrupt enable pin
#define LIMIT_INT_vect PCINT0_vect // hard/soft limit not ported #define LIMIT_INT_vect PCINT0_vect
#define LIMIT_PCMSK PCMSK0 // Pin change interrupt register // hard/soft limit not ported #define LIMIT_PCMSK PCMSK0 // Pin change interrupt register
// Define spindle enable and spindle direction output pins. // Define spindle enable and spindle direction output pins.
#define SPINDLE_ENABLE_DDR DDRB #define SPINDLE_ENABLE_DDR DDRB

10
grbl/limits.c
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@ -41,8 +41,8 @@ void limits_init()
#endif #endif
if (bit_istrue(settings.flags,BITFLAG_HARD_LIMIT_ENABLE)) { if (bit_istrue(settings.flags,BITFLAG_HARD_LIMIT_ENABLE)) {
LIMIT_PCMSK |= LIMIT_MASK; // Enable specific pins of the Pin Change Interrupt //LIMIT_PCMSK |= LIMIT_MASK; // Enable specific pins of the Pin Change Interrupt
PCICR |= (1 << LIMIT_INT); // Enable Pin Change Interrupt //PCICR |= (1 << LIMIT_INT); // Enable Pin Change Interrupt
} else { } else {
limits_disable(); limits_disable();
} }
@ -58,8 +58,8 @@ void limits_init()
// Disables hard limits. // Disables hard limits.
void limits_disable() void limits_disable()
{ {
LIMIT_PCMSK &= ~LIMIT_MASK; // Disable specific pins of the Pin Change Interrupt //LIMIT_PCMSK &= ~LIMIT_MASK; // Disable specific pins of the Pin Change Interrupt
PCICR &= ~(1 << LIMIT_INT); // Disable Pin Change Interrupt //PCICR &= ~(1 << LIMIT_INT); // Disable Pin Change Interrupt
} }
@ -69,7 +69,7 @@ void limits_disable()
uint8_t limits_get_state() uint8_t limits_get_state()
{ {
uint8_t limit_state = 0; uint8_t limit_state = 0;
uint8_t pin = (LIMIT_PIN & LIMIT_MASK); uint32_t pin = (LIMIT_PIN & LIMIT_MASK);
#ifdef INVERT_LIMIT_PIN_MASK #ifdef INVERT_LIMIT_PIN_MASK
pin ^= INVERT_LIMIT_PIN_MASK; pin ^= INVERT_LIMIT_PIN_MASK;
#endif #endif

2
grbl/settings.c
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@ -335,7 +335,7 @@ uint32_t get_direction_pin_mask(uint8_t axis_idx)
// Returns limit pin mask according to Grbl internal axis indexing. // Returns limit pin mask according to Grbl internal axis indexing.
uint8_t get_limit_pin_mask(uint8_t axis_idx) uint32_t get_limit_pin_mask(uint8_t axis_idx)
{ {
if ( axis_idx == X_AXIS ) { return((1<<X_LIMIT_BIT)); } if ( axis_idx == X_AXIS ) { return((1<<X_LIMIT_BIT)); }
if ( axis_idx == Y_AXIS ) { return((1<<Y_LIMIT_BIT)); } if ( axis_idx == Y_AXIS ) { return((1<<Y_LIMIT_BIT)); }

2
grbl/settings.h
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@ -138,7 +138,7 @@ uint32_t get_step_pin_mask(uint8_t i);
uint32_t get_direction_pin_mask(uint8_t i); uint32_t get_direction_pin_mask(uint8_t i);
// Returns the limit pin mask according to Grbl's internal axis numbering // Returns the limit pin mask according to Grbl's internal axis numbering
uint8_t get_limit_pin_mask(uint8_t i); uint32_t get_limit_pin_mask(uint8_t i);
#endif #endif