Clean up dummy regs
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Todd Fleming
parent
3ebbfa4dd3
commit
b1d83c2892
@ -8,64 +8,7 @@ struct DummyReg {
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uint8_t operator|=(uint8_t x) {return *this = *this | x;}
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};
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extern DummyReg DDRA;
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extern DummyReg DDRB;
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extern DummyReg DDRC;
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extern DummyReg DDRD;
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extern DummyReg PORTA;
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extern DummyReg PORTB;
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extern DummyReg PORTC;
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extern DummyReg PORTD;
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extern DummyReg PINA;
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extern DummyReg PINB;
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extern DummyReg PINC;
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extern DummyReg PIND;
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extern DummyReg EEAR;
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extern DummyReg EECR;
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extern DummyReg EEDR;
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extern DummyReg EEMPE;
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extern DummyReg EEPE;
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extern DummyReg OCR2A;
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extern DummyReg NotUsed;
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extern DummyReg PCICR;
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extern DummyReg PCIE0;
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extern DummyReg PCIE1;
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extern DummyReg PCMSK0;
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extern DummyReg PCMSK1;
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extern DummyReg TCCR2A;
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extern DummyReg TCCR2B;
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extern DummyReg UCSR0A;
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extern DummyReg UCSR0B;
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extern DummyReg U2X0;
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extern DummyReg UBRR0H;
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extern DummyReg UBRR0L;
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extern DummyReg UDR0;
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static const int COM1A0 = 0;
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static const int COM1A1 = 0;
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static const int COM1B0 = 0;
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static const int COM1B1 = 0;
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static const int COM2A0 = 0;
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static const int COM2A1 = 0;
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static const int COM2B0 = 0;
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static const int COM2B1 = 0;
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static const int CS22 = 0;
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static const int EEMWE = 0;
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static const int EERE = 0;
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static const int EEWE = 0;
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static const int WGM10 = 0;
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static const int WGM11 = 0;
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static const int WGM12 = 0;
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static const int WGM13 = 0;
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static const int WGM20 = 0;
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static const int WGM21 = 0;
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static const int RXEN0 = 0;
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static const int TXEN0 = 0;
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static const int RXCIE0 = 0;
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static const int UDRIE0 = 0;
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@ -677,32 +677,32 @@
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*/
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// Define flood and mist coolant enable output pins.
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#define COOLANT_FLOOD_DDR DDRC
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#define COOLANT_FLOOD_PORT PORTC
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#define COOLANT_FLOOD_DDR NotUsed
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#define COOLANT_FLOOD_PORT NotUsed
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#define COOLANT_FLOOD_BIT 3 // Uno Analog Pin 3
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#define COOLANT_MIST_DDR DDRC
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#define COOLANT_MIST_PORT PORTC
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#define COOLANT_MIST_DDR NotUsed
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#define COOLANT_MIST_PORT NotUsed
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#define COOLANT_MIST_BIT 4 // Uno Analog Pin 3
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// Define user-control controls (cycle start, reset, feed hold) input pins.
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// NOTE: All CONTROLs pins must be on the same port and not on a port with other input pins (limits).
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#define CONTROL_DDR DDRC
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#define CONTROL_PIN PINC
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#define CONTROL_PORT PORTC
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#define CONTROL_DDR NotUsed
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#define CONTROL_PIN NotUsed
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#define CONTROL_PORT NotUsed
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#define CONTROL_RESET_BIT 0 // Uno Analog Pin 0
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#define CONTROL_FEED_HOLD_BIT 1 // Uno Analog Pin 1
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#define CONTROL_CYCLE_START_BIT 2 // Uno Analog Pin 2
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#define CONTROL_SAFETY_DOOR_BIT 1 // Uno Analog Pin 1 NOTE: Safety door is shared with feed hold. Enabled by config define.
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#define CONTROL_INT PCIE1 // Pin change interrupt enable pin
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#define CONTROL_INT_vect PCINT1_vect
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#define CONTROL_PCMSK PCMSK1 // Pin change interrupt register
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#define CONTROL_PCMSK NotUsed // Pin change interrupt register
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#define CONTROL_MASK ((1<<CONTROL_RESET_BIT)|(1<<CONTROL_FEED_HOLD_BIT)|(1<<CONTROL_CYCLE_START_BIT)|(1<<CONTROL_SAFETY_DOOR_BIT))
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#define CONTROL_INVERT_MASK CONTROL_MASK // May be re-defined to only invert certain control pins.
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// Define probe switch input pin.
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#define PROBE_DDR DDRC
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#define PROBE_PIN PINC
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#define PROBE_PORT PORTC
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#define PROBE_DDR NotUsed
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#define PROBE_PIN NotUsed
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#define PROBE_PORT NotUsed
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#define PROBE_BIT 5 // Uno Analog Pin 5
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#define PROBE_MASK (1<<PROBE_BIT)
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38
grbl/main.c
38
grbl/main.c
@ -24,41 +24,9 @@
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void isr_init();
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/*Holding space for dummy registers*/
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DummyReg DDRA;
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DummyReg DDRB;
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DummyReg DDRC;
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DummyReg DDRD;
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DummyReg PORTA;
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DummyReg PORTB;
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DummyReg PORTC;
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DummyReg PORTD;
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DummyReg PINA;
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DummyReg PINB;
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DummyReg PINC;
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DummyReg PIND;
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DummyReg EEAR;
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DummyReg EECR;
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DummyReg EEDR;
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DummyReg EEMPE;
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DummyReg EEPE;
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DummyReg OCR2A;
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DummyReg PCICR;
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DummyReg PCIE0;
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DummyReg PCIE1;
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DummyReg PCMSK0;
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DummyReg PCMSK1;
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DummyReg TCCR2A;
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DummyReg TCCR2B;
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DummyReg UCSR0A;
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DummyReg UCSR0B;
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DummyReg U2X0;
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DummyReg UBRR0H;
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DummyReg UBRR0L;
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DummyReg UDR0;
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extern DummyReg NotUsed;
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extern DummyReg PCICR;
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extern DummyReg PCIE1;
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// Declare system global variable structure
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system_t sys;
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@ -112,6 +112,7 @@ void serial_init()
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#endif
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}
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/*
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void legacy_serial_init()
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{
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// Set baud rate
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@ -130,6 +131,7 @@ void legacy_serial_init()
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// defaults to 8-bit, no parity, 1 stop bit
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}
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*/
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// Writes one byte to the TX serial buffer. Called by main program.
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void serial_write(uint8_t data) {
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@ -154,7 +156,7 @@ void serial_write(uint8_t data) {
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serialDriver.Send(serial_tx_buffer, 1);
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#endif
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}
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/*
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// Writes one byte to the TX serial buffer. Called by main program.
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void legacy_serial_write(uint8_t data) {
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// Calculate next head
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@ -174,7 +176,7 @@ void legacy_serial_write(uint8_t data) {
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// Enable Data Register Empty Interrupt to make sure tx-streaming is running
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UCSR0B |= (1 << UDRIE0);
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}
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*/
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//Device driver interrupt
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// The CMSIS Driver doesn't have seperate interrupts/callbacks available for TX and RX but instead
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// is a single composite interrupt.
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@ -190,6 +192,7 @@ void serialInterrupt(uint32_t event) {
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//We don't use TX interrupts directly with the ARM Driver.
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// Data Register Empty Interrupt handler
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/*
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void legacy_TX_ISR(void* SERIAL_UDRE)
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{
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uint8_t tail = serial_tx_buffer_tail; // Temporary serial_tx_buffer_tail (to optimize for volatile)
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@ -206,7 +209,7 @@ void legacy_TX_ISR(void* SERIAL_UDRE)
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// Turn off Data Register Empty Interrupt to stop tx-streaming if this concludes the transfer
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if (tail == serial_tx_buffer_head) { UCSR0B &= ~(1 << UDRIE0); }
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}
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*/
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// Fetches the first byte in the serial read buffer. Called by main program.
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uint8_t serial_read()
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