ManuelW/grbl-LPC-CoreXY
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Clean up dummy regs

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This commit is contained in:
Todd Fleming 2017-01-17 14:46:12 -05:00
parent 3ebbfa4dd3
commit b1d83c2892
4 changed files with 21 additions and 107 deletions
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59
grbl-lpc/avr/io.h
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@ -8,64 +8,7 @@ struct DummyReg {
uint8_t operator|=(uint8_t x) {return *this = *this | x;} uint8_t operator|=(uint8_t x) {return *this = *this | x;}
}; };
extern DummyReg DDRA; extern DummyReg NotUsed;
extern DummyReg DDRB;
extern DummyReg DDRC;
extern DummyReg DDRD;
extern DummyReg PORTA;
extern DummyReg PORTB;
extern DummyReg PORTC;
extern DummyReg PORTD;
extern DummyReg PINA;
extern DummyReg PINB;
extern DummyReg PINC;
extern DummyReg PIND;
extern DummyReg EEAR;
extern DummyReg EECR;
extern DummyReg EEDR;
extern DummyReg EEMPE;
extern DummyReg EEPE;
extern DummyReg OCR2A;
extern DummyReg PCICR; extern DummyReg PCICR;
extern DummyReg PCIE0;
extern DummyReg PCIE1; extern DummyReg PCIE1;
extern DummyReg PCMSK0;
extern DummyReg PCMSK1;
extern DummyReg TCCR2A;
extern DummyReg TCCR2B;
extern DummyReg UCSR0A;
extern DummyReg UCSR0B;
extern DummyReg U2X0;
extern DummyReg UBRR0H;
extern DummyReg UBRR0L;
extern DummyReg UDR0;
static const int COM1A0 = 0;
static const int COM1A1 = 0;
static const int COM1B0 = 0;
static const int COM1B1 = 0;
static const int COM2A0 = 0;
static const int COM2A1 = 0;
static const int COM2B0 = 0;
static const int COM2B1 = 0;
static const int CS22 = 0;
static const int EEMWE = 0;
static const int EERE = 0;
static const int EEWE = 0;
static const int WGM10 = 0;
static const int WGM11 = 0;
static const int WGM12 = 0;
static const int WGM13 = 0;
static const int WGM20 = 0;
static const int WGM21 = 0;
static const int RXEN0 = 0;
static const int TXEN0 = 0;
static const int RXCIE0 = 0;
static const int UDRIE0 = 0;

22
grbl/config.h
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@ -677,32 +677,32 @@
*/ */
// Define flood and mist coolant enable output pins. // Define flood and mist coolant enable output pins.
#define COOLANT_FLOOD_DDR DDRC #define COOLANT_FLOOD_DDR NotUsed
#define COOLANT_FLOOD_PORT PORTC #define COOLANT_FLOOD_PORT NotUsed
#define COOLANT_FLOOD_BIT 3 // Uno Analog Pin 3 #define COOLANT_FLOOD_BIT 3 // Uno Analog Pin 3
#define COOLANT_MIST_DDR DDRC #define COOLANT_MIST_DDR NotUsed
#define COOLANT_MIST_PORT PORTC #define COOLANT_MIST_PORT NotUsed
#define COOLANT_MIST_BIT 4 // Uno Analog Pin 3 #define COOLANT_MIST_BIT 4 // Uno Analog Pin 3
// Define user-control controls (cycle start, reset, feed hold) input pins. // Define user-control controls (cycle start, reset, feed hold) input pins.
// NOTE: All CONTROLs pins must be on the same port and not on a port with other input pins (limits). // NOTE: All CONTROLs pins must be on the same port and not on a port with other input pins (limits).
#define CONTROL_DDR DDRC #define CONTROL_DDR NotUsed
#define CONTROL_PIN PINC #define CONTROL_PIN NotUsed
#define CONTROL_PORT PORTC #define CONTROL_PORT NotUsed
#define CONTROL_RESET_BIT 0 // Uno Analog Pin 0 #define CONTROL_RESET_BIT 0 // Uno Analog Pin 0
#define CONTROL_FEED_HOLD_BIT 1 // Uno Analog Pin 1 #define CONTROL_FEED_HOLD_BIT 1 // Uno Analog Pin 1
#define CONTROL_CYCLE_START_BIT 2 // Uno Analog Pin 2 #define CONTROL_CYCLE_START_BIT 2 // Uno Analog Pin 2
#define CONTROL_SAFETY_DOOR_BIT 1 // Uno Analog Pin 1 NOTE: Safety door is shared with feed hold. Enabled by config define. #define CONTROL_SAFETY_DOOR_BIT 1 // Uno Analog Pin 1 NOTE: Safety door is shared with feed hold. Enabled by config define.
#define CONTROL_INT PCIE1 // Pin change interrupt enable pin #define CONTROL_INT PCIE1 // Pin change interrupt enable pin
#define CONTROL_INT_vect PCINT1_vect #define CONTROL_INT_vect PCINT1_vect
#define CONTROL_PCMSK PCMSK1 // Pin change interrupt register #define CONTROL_PCMSK NotUsed // Pin change interrupt register
#define CONTROL_MASK ((1<<CONTROL_RESET_BIT)|(1<<CONTROL_FEED_HOLD_BIT)|(1<<CONTROL_CYCLE_START_BIT)|(1<<CONTROL_SAFETY_DOOR_BIT)) #define CONTROL_MASK ((1<<CONTROL_RESET_BIT)|(1<<CONTROL_FEED_HOLD_BIT)|(1<<CONTROL_CYCLE_START_BIT)|(1<<CONTROL_SAFETY_DOOR_BIT))
#define CONTROL_INVERT_MASK CONTROL_MASK // May be re-defined to only invert certain control pins. #define CONTROL_INVERT_MASK CONTROL_MASK // May be re-defined to only invert certain control pins.
// Define probe switch input pin. // Define probe switch input pin.
#define PROBE_DDR DDRC #define PROBE_DDR NotUsed
#define PROBE_PIN PINC #define PROBE_PIN NotUsed
#define PROBE_PORT PORTC #define PROBE_PORT NotUsed
#define PROBE_BIT 5 // Uno Analog Pin 5 #define PROBE_BIT 5 // Uno Analog Pin 5
#define PROBE_MASK (1<<PROBE_BIT) #define PROBE_MASK (1<<PROBE_BIT)

38
grbl/main.c
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@ -24,41 +24,9 @@
void isr_init(); void isr_init();
/*Holding space for dummy registers*/ /*Holding space for dummy registers*/
DummyReg DDRA; extern DummyReg NotUsed;
DummyReg DDRB; extern DummyReg PCICR;
DummyReg DDRC; extern DummyReg PCIE1;
DummyReg DDRD;
DummyReg PORTA;
DummyReg PORTB;
DummyReg PORTC;
DummyReg PORTD;
DummyReg PINA;
DummyReg PINB;
DummyReg PINC;
DummyReg PIND;
DummyReg EEAR;
DummyReg EECR;
DummyReg EEDR;
DummyReg EEMPE;
DummyReg EEPE;
DummyReg OCR2A;
DummyReg PCICR;
DummyReg PCIE0;
DummyReg PCIE1;
DummyReg PCMSK0;
DummyReg PCMSK1;
DummyReg TCCR2A;
DummyReg TCCR2B;
DummyReg UCSR0A;
DummyReg UCSR0B;
DummyReg U2X0;
DummyReg UBRR0H;
DummyReg UBRR0L;
DummyReg UDR0;
// Declare system global variable structure // Declare system global variable structure
system_t sys; system_t sys;

9
grbl/serial.c
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@ -112,6 +112,7 @@ void serial_init()
#endif #endif
} }
/*
void legacy_serial_init() void legacy_serial_init()
{ {
// Set baud rate // Set baud rate
@ -130,6 +131,7 @@ void legacy_serial_init()
// defaults to 8-bit, no parity, 1 stop bit // defaults to 8-bit, no parity, 1 stop bit
} }
*/
// Writes one byte to the TX serial buffer. Called by main program. // Writes one byte to the TX serial buffer. Called by main program.
void serial_write(uint8_t data) { void serial_write(uint8_t data) {
@ -154,7 +156,7 @@ void serial_write(uint8_t data) {
serialDriver.Send(serial_tx_buffer, 1); serialDriver.Send(serial_tx_buffer, 1);
#endif #endif
} }
/*
// Writes one byte to the TX serial buffer. Called by main program. // Writes one byte to the TX serial buffer. Called by main program.
void legacy_serial_write(uint8_t data) { void legacy_serial_write(uint8_t data) {
// Calculate next head // Calculate next head
@ -174,7 +176,7 @@ void legacy_serial_write(uint8_t data) {
// Enable Data Register Empty Interrupt to make sure tx-streaming is running // Enable Data Register Empty Interrupt to make sure tx-streaming is running
UCSR0B |= (1 << UDRIE0); UCSR0B |= (1 << UDRIE0);
} }
*/
//Device driver interrupt //Device driver interrupt
// The CMSIS Driver doesn't have seperate interrupts/callbacks available for TX and RX but instead // The CMSIS Driver doesn't have seperate interrupts/callbacks available for TX and RX but instead
// is a single composite interrupt. // is a single composite interrupt.
@ -190,6 +192,7 @@ void serialInterrupt(uint32_t event) {
//We don't use TX interrupts directly with the ARM Driver. //We don't use TX interrupts directly with the ARM Driver.
// Data Register Empty Interrupt handler // Data Register Empty Interrupt handler
/*
void legacy_TX_ISR(void* SERIAL_UDRE) void legacy_TX_ISR(void* SERIAL_UDRE)
{ {
uint8_t tail = serial_tx_buffer_tail; // Temporary serial_tx_buffer_tail (to optimize for volatile) uint8_t tail = serial_tx_buffer_tail; // Temporary serial_tx_buffer_tail (to optimize for volatile)
@ -206,7 +209,7 @@ void legacy_TX_ISR(void* SERIAL_UDRE)
// Turn off Data Register Empty Interrupt to stop tx-streaming if this concludes the transfer // Turn off Data Register Empty Interrupt to stop tx-streaming if this concludes the transfer
if (tail == serial_tx_buffer_head) { UCSR0B &= ~(1 << UDRIE0); } if (tail == serial_tx_buffer_head) { UCSR0B &= ~(1 << UDRIE0); }
} }
*/
// Fetches the first byte in the serial read buffer. Called by main program. // Fetches the first byte in the serial read buffer. Called by main program.
uint8_t serial_read() uint8_t serial_read()