Bug fixes for timers, added some wdt support for limit debounce.
- Typo in timer def, - Handle 8 bit timers correctly, - Don't skip TOP count in CTC mode - added SREG for atomic bit operations
This commit is contained in:
ashelly
@ -22,12 +22,14 @@
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#include "interrupt.h"
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#include "io.h"
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#include "wdt.h"
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//pseudo-Interrupt vector table
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//pseudo-Interrupt vector table
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isr_fp compa_vect[6]={0};
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isr_fp compb_vect[6]={0};
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isr_fp ovf_vect[6]={0};
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isr_fp wdt_vect = 0;
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isr_fp pc_vect = 0;
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void sei() {io.sreg|=SEI;}
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void cli() {io.sreg&=~SEI;}
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@ -45,91 +47,108 @@ enum sim_wgm_mode {
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wgm_RESERVED
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};
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enum sim_wgm_mode sim_wgm0[4] = {wgm_NORMAL,wgm_PHASE_PWM,wgm_CTC,wgm_FAST_PWM};
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enum sim_wgm_mode sim_wgmN[8] = {wgm_NORMAL,wgm_PHASE_PWM,wgm_PHASE_PWM,wgm_PH_F_PWM,
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wgm_CTC, wgm_FAST_PWM, wgm_FAST_PWM, wgm_FAST_PWM};
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//3-bit wgm table for 8-bit timers
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enum sim_wgm_mode sim_wgm_3[] = {wgm_NORMAL,wgm_PHASE_PWM,wgm_CTC,wgm_FAST_PWM,
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wgm_RESERVED,wgm_PHASE_PWM, wgm_RESERVED, wgm_FAST_PWM};
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//4-bit wgm modes for 16-bit timers
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enum sim_wgm_mode sim_wgm_4[16] = {wgm_NORMAL,wgm_PHASE_PWM,wgm_PHASE_PWM,wgm_PHASE_PWM,
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wgm_CTC, wgm_FAST_PWM, wgm_FAST_PWM, wgm_FAST_PWM,
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wgm_PH_F_PWM, wgm_PH_F_PWM, wgm_PHASE_PWM, wgm_PHASE_PWM,
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wgm_CTC, wgm_RESERVED, wgm_FAST_PWM, wgm_FAST_PWM};
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static const uint16_t timer_bitdepth[SIM_N_TIMERS] = {
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0xFF,0xFFFF,0xFF,
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//0xFFFF,0xFFFF,0xFFFF 3 more for mega
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};
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void timer_interrupts() {
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int i;
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uint8_t ien = io.sreg&SEI; //interrupts enabled?
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io.prescaler++;
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//all clocks
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for (i=0;i<2;i++){
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for (i=0;i<SIM_N_TIMERS;i++){
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uint8_t cs = io.tccrb[i]&7; //clock select bits
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int16_t increment = sim_scaling[cs];
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uint16_t bitmask = timer_bitdepth[i];
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uint8_t cs = io.tccrb[i]&7; //clock select bits
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int16_t increment = sim_scaling[cs];
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//check scaling to see if timer fires
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if (increment && (io.prescaler&(increment-1))==0) {
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//check scaling to see if timer fires
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if (increment && (io.prescaler&(increment-1))==0) {
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//select waveform generation mode
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enum sim_wgm_mode mode;
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if (i==0 || i==2) { //(T0 and T2 are different from rest)
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uint8_t wgm = io.tccra[i]&3; //look at low 2 bits
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mode = sim_wgm0[wgm];
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}
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else {
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uint8_t wgm = ((io.tccrb[i]&8)>>1) | (io.tccra[i]&3); //only using 3 bits for now
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mode = sim_wgmN[wgm];
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}
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//tick
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io.tcnt[i]++;
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//comparators
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if ((io.timsk[i]&(1<<SIM_OCA)) && io.tcnt[i]==io.ocra[i]) io.tifr[i]|=(1<<SIM_OCA);
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if ((io.timsk[i]&(1<<SIM_OCB)) && io.tcnt[i]==io.ocrb[i]) io.tifr[i]|=(1<<SIM_OCB);
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if ((io.timsk[i]&(1<<SIM_OCC)) && io.tcnt[i]==io.ocrc[i]) io.tifr[i]|=(1<<SIM_OCC);
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//select waveform generation mode
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enum sim_wgm_mode mode;
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if (i==0 || i==2) { //(T0 and T2 use only 3 wgm bits)
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uint8_t wgm = ((io.tccrb[i]&0x08)>>1) | (io.tccra[i]&3);
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mode = sim_wgm_3[wgm];
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}
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else {
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uint8_t wgm = ((io.tccrb[i]&0x18)>>1) | (io.tccra[i]&3); //4 wgm bits
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mode = sim_wgm_4[wgm];
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}
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switch (mode) {
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case wgm_NORMAL: //Normal mode
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if (i==0) io.tcnt[i]&=0xFF; //timer0 is 8 bit;
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if (i==2) io.tcnt[i]&=0xFF; //timer2 is 8 bit;
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if (io.tcnt[i]==0) io.tifr[i]|=(1<<SIM_TOV);
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break;
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//tick
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if (io.tifr[i]&(1<<SIM_ROLL)) { //handle CTC mode rollover
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io.tcnt[i]=0;
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io.tifr[i]&=~(1<<SIM_ROLL);
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}
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else {
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io.tcnt[i]++;
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}
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io.tcnt[i]&=bitmask; //limit the 8 bit timers
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case wgm_CTC: //CTC mode
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if (io.tcnt[i]==io.ocra[i]) io.tcnt[i]=0;
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break;
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default: //unsupported
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break;
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}
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//call any triggered interupts
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if (ien && io.tifr[i]) {
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if (compa_vect[i] && (io.tifr[i]&(1<<SIM_OCA))) {
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compa_vect[i]();
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io.tifr[i]&=~(1<<SIM_OCA);
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//TODO: insert port_monitor call here
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}
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if (compb_vect[i] && (io.tifr[i]&(1<<SIM_OCB))) {
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compb_vect[i]();
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io.tifr[i]&=~(1<<SIM_OCB);
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}
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if (ovf_vect[i] && (io.tifr[i]&(1<<SIM_TOV))) {
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ovf_vect[i]();
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io.tifr[i]&=~(1<<SIM_TOV);
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}
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}
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}
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switch (mode) {
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case wgm_NORMAL: //Normal mode, ovf on rollover
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if (io.tcnt[i]==0) io.tifr[i]|=(1<<SIM_TOV); //overflow
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break;
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case wgm_CTC: //CTC mode, ovf at TOP, 0 next tick
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if (io.tcnt[i]==(io.ocra[i]&bitmask)) {
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io.tifr[i]|=(1<<SIM_TOV)|(1<<SIM_ROLL); //overflow
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}
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break;
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default: //unsupported
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break;
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}
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//comparators
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if ((io.timsk[i]&(1<<SIM_OCA)) && io.tcnt[i]==(io.ocra[i]&bitmask)) io.tifr[i]|=(1<<SIM_OCA);
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if ((io.timsk[i]&(1<<SIM_OCB)) && io.tcnt[i]==(io.ocrb[i]&bitmask)) io.tifr[i]|=(1<<SIM_OCB);
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if ((io.timsk[i]&(1<<SIM_OCC)) && io.tcnt[i]==(io.ocrc[i]&bitmask)) io.tifr[i]|=(1<<SIM_OCC);
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//call any triggered interupts
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if (ien && io.tifr[i]) {
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if (compa_vect[i] && (io.tifr[i]&(1<<SIM_OCA))) {
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compa_vect[i]();
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io.tifr[i]&=~(1<<SIM_OCA);
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//TODO: insert port_monitor call here
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}
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if (compb_vect[i] && (io.tifr[i]&(1<<SIM_OCB))) {
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compb_vect[i]();
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io.tifr[i]&=~(1<<SIM_OCB);
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}
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if (ovf_vect[i] && (io.tifr[i]&(1<<SIM_TOV))) {
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ovf_vect[i]();
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io.tifr[i]&=~(1<<SIM_TOV);
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}
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}
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}
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}
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//// TODO for more complete timer sim.
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// pwm modes. (only used for variable spindle, I think).
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//// TODO for more complete timer sim.
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// pwm modes. (only used for variable spindle, I think).
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// -- would require fixing wgm mode for Timers1..5
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// -- phase correct modes need updown counter.
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// output pins (also only for variable spindle, I think).
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//// Other chip features not needed yet for grbl:
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// writes to TCNT0 prevent compare match (need write detector.)
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// writes to TCNT0 prevent compare match (need write detector.)
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// force output compare (unused)
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// input capture (unused and how would we signal it?)
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// define the other output compare registers.
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// usercode can clear unhandled interrupt flags by writing 1.
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// usercode can clear unhandled interrupt flags by writing 1.
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// --(this may be impossible, since bit was 1 before the write.)
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// prescaler reset.
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// maybe need to cli on interrupt entry
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}
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@ -28,12 +28,14 @@
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//#define TIMER1_COMPA_vect
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#define ISR(a) void interrupt_ ## a ()
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// Stub of the timer interrupt functions we need
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// Stubs of the hardware interrupt functions we are using
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void interrupt_TIMER0_COMPA_vect();
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void interrupt_TIMER1_COMPA_vect();
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void interrupt_TIMER0_OVF_vect();
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void interrupt_SERIAL_UDRE();
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void interrupt_SERIAL_RX();
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void interrupt_LIMIT_INT_vect();
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void interrupt_WDT_vect();
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//pseudo-Interrupt vector table
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@ -41,7 +43,8 @@ typedef void(*isr_fp)(void);
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extern isr_fp compa_vect[6];
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extern isr_fp compb_vect[6];
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extern isr_fp ovf_vect[6];
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extern isr_fp wdt_vect;
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extern isr_fp pc_vect; //pin change
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// enable interrupts now does something in the simulation environment
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#define SEI 0x80
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@ -52,5 +55,4 @@ void cli();
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void timer_interrupts();
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#endif
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33
sim/avr/io.h
33
sim/avr/io.h
@ -4,7 +4,7 @@
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Part of Grbl Simulator
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Copyright (c) 2012 Jens Geisler
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Copyright (c) 2012-2104 Jens Geisler, Adam Shelly
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Grbl is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -40,7 +40,7 @@ enum {
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SIM_PORT_COUNT
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};
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#define SIM_N_TIMERS 6
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#define SIM_N_TIMERS 3 //328p has 3, Mega has 6
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// dummy register variables
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@ -60,12 +60,14 @@ typedef struct io_sim {
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uint8_t pcmsk[3];
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uint8_t ucsr0[3];
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uint8_t udr[3];
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uint8_t gpior[3];
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uint8_t mcusr;
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uint8_t wdtcsr;
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union hilo16 ubrr0;
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uint16_t prescaler; //continuously running
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uint8_t sreg;
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} io_sim_t;
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volatile extern io_sim_t io;
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@ -94,6 +96,8 @@ volatile extern io_sim_t io;
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#define DDRG io.ddr[SIM_G]
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#define DDRH io.ddr[SIM_H]
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#define DDRJ io.ddr[SIM_J]
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#define DDRK io.ddr[SIM_K]
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#define DDRL io.ddr[SIM_L]
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#define PINA io.pin[SIM_A]
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#define PINB io.pin[SIM_B]
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@ -121,6 +125,7 @@ volatile extern io_sim_t io;
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#define SIM_OCB 2
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#define SIM_OCC 3
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#define SIM_ICI 5
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#define SIM_ROLL 7 //stealing reserved TIFR bit
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#define OCIE0A SIM_OCA
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#define OCIE0B SIM_OCB
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@ -148,8 +153,8 @@ volatile extern io_sim_t io;
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#define TCNT1 io.tcnt[1]
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#define TCNT2 io.tcnt[2]
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#define TCCR0B io.tccra[0]
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#define TCCR0A io.tccrb[0]
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#define TCCR0A io.tccra[0]
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#define TCCR0B io.tccrb[0]
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#define TCCR1A io.tccra[1]
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#define TCCR1B io.tccrb[1]
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#define TCCR2A io.tccra[2]
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@ -179,6 +184,7 @@ volatile extern io_sim_t io;
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#define PCICR io.pcicr
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#define PCIE0 0
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#define PCIE1 1
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#define PCIE2 2
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//serial channel
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#define UCSR0A io.ucsr0[SIM_A]
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@ -196,6 +202,23 @@ volatile extern io_sim_t io;
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#define PCMSK1 io.pcmsk[1]
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#define PCMSK2 io.pcmsk[2]
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//GPIO
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#define GPIOR0 io.gpior[0]
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#define GPIOR1 io.gpior[1]
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#define GPIOR2 io.gpior[2]
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//MCU Status
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#define MCUSR io.mcusr
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#define PORF 0
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#define EXTRF 1
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#define BORF 2
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#define WDRF 3
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#define JTRF 4
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//Interrupt Status
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#define SREG io.sreg
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#endif
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@ -1 +1,11 @@
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#define WDTCSR wdt
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#define WDP0 0
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#define WDP1 1
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#define WDP2 2
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#define WDE 3
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#define WDCE 4
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#define WDP3 5
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#define WDIE 6
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#define WDIF 7
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uint16_t wdt;
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