9b37637ae6
- Typo in timer def, - Handle 8 bit timers correctly, - Don't skip TOP count in CTC mode - added SREG for atomic bit operations
225 lines
4.8 KiB
C
225 lines
4.8 KiB
C
/*
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interrupt.h - replacement for the avr include of the same name to provide
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dummy register variables and macros
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Part of Grbl Simulator
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Copyright (c) 2012-2104 Jens Geisler, Adam Shelly
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Grbl is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Grbl is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Grbl. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef io_h
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#define io_h
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#include <inttypes.h>
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union hilo16 {
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uint16_t w;
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struct {
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uint8_t l; //TODO: check that these are right order on x86. Doesn't matter for current usage, but might someday
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uint8_t h;
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};
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};
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enum {
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SIM_A, SIM_B, SIM_C, SIM_D, SIM_E,
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SIM_F, SIM_G, SIM_H, SIM_J, SIM_K, SIM_L,
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SIM_PORT_COUNT
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};
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#define SIM_N_TIMERS 3 //328p has 3, Mega has 6
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// dummy register variables
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typedef struct io_sim {
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uint8_t ddr[SIM_PORT_COUNT];
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uint8_t port[SIM_PORT_COUNT];
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uint8_t pin[SIM_PORT_COUNT];
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uint8_t timsk[SIM_N_TIMERS];
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uint16_t ocra[SIM_N_TIMERS];
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uint16_t ocrb[SIM_N_TIMERS];
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uint16_t ocrc[SIM_N_TIMERS];
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uint16_t tcnt[SIM_N_TIMERS]; //tcint0 is really only 8bit
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uint8_t tccra[SIM_N_TIMERS];
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uint8_t tccrb[SIM_N_TIMERS];
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uint8_t tifr[SIM_N_TIMERS];
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uint8_t pcicr;
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uint8_t pcmsk[3];
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uint8_t ucsr0[3];
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uint8_t udr[3];
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uint8_t gpior[3];
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uint8_t mcusr;
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uint8_t wdtcsr;
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union hilo16 ubrr0;
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uint16_t prescaler; //continuously running
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uint8_t sreg;
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} io_sim_t;
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volatile extern io_sim_t io;
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// dummy macros for interrupt related registers
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#define PORTA io.port[SIM_A]
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#define PORTB io.port[SIM_B]
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#define PORTC io.port[SIM_C]
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#define PORTD io.port[SIM_D]
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#define PORTE io.port[SIM_E]
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#define PORTF io.port[SIM_F]
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#define PORTG io.port[SIM_G]
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#define PORTH io.port[SIM_H]
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#define PORTJ io.port[SIM_J]
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#define PORTK io.port[SIM_K]
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#define PORTL io.port[SIM_L]
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#define DDRA io.ddr[SIM_A]
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#define DDRB io.ddr[SIM_B]
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#define DDRC io.ddr[SIM_C]
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#define DDRD io.ddr[SIM_D]
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#define DDRE io.ddr[SIM_E]
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#define DDRF io.ddr[SIM_F]
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#define DDRG io.ddr[SIM_G]
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#define DDRH io.ddr[SIM_H]
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#define DDRJ io.ddr[SIM_J]
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#define DDRK io.ddr[SIM_K]
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#define DDRL io.ddr[SIM_L]
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#define PINA io.pin[SIM_A]
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#define PINB io.pin[SIM_B]
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#define PINC io.pin[SIM_C]
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#define PIND io.pin[SIM_D]
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#define PINE io.pin[SIM_E]
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#define PINF io.pin[SIM_F]
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#define PING io.pin[SIM_G]
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#define PINH io.pin[SIM_H]
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#define PINJ io.pin[SIM_J]
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#define PINK io.pin[SIM_K]
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#define PINL io.pin[SIM_L]
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#define TIMSK0 io.timsk[0]
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#define TIMSK1 io.timsk[1]
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#define TIMSK2 io.timsk[2]
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#define TIMSK3 io.timsk[3]
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#define TIMSK4 io.timsk[4]
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#define TIMSK5 io.timsk[5]
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#define SIM_TOV 0
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#define SIM_OCA 1
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#define SIM_OCB 2
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#define SIM_OCC 3
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#define SIM_ICI 5
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#define SIM_ROLL 7 //stealing reserved TIFR bit
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#define OCIE0A SIM_OCA
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#define OCIE0B SIM_OCB
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#define TOIE0 SIM_TOV
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#define ICIE1 SIM_ICI
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#define OCIE1C SIM_OCC
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#define OCIE1B SIM_OCB
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#define OCIE1A SIM_OCA
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#define TOIE1 SIM_ICI
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#define ICIE2 SIM_ICI
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#define OCIE2C SIM_OCC
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#define OCIE2B SIM_OCB
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#define OCIE2A SIM_OCA
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#define TOIE2 SIM_TOV
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#define OCR0A io.ocra[0]
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#define OCR1A io.ocra[1]
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#define OCR2A io.ocra[2]
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//There are more..
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#define TCNT0 io.tcnt[0]
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#define TCNT1 io.tcnt[1]
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#define TCNT2 io.tcnt[2]
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#define TCCR0A io.tccra[0]
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#define TCCR0B io.tccrb[0]
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#define TCCR1A io.tccra[1]
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#define TCCR1B io.tccrb[1]
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#define TCCR2A io.tccra[2]
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#define TCCR2B io.tccrb[2]
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#define CS00 0
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#define CS01 1
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#define CS12 2
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#define CS11 1
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#define CS10 0
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#define CS21 1
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#define WGM13 4
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#define WGM12 3
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#define WGM11 1
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#define WGM10 0
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#define WGM21 1
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#define COM1A1 7
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#define COM1A0 6
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#define COM1B1 5
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#define COM1B0 4
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#define COM1C1 3
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#define COM1C0 2
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#define PCICR io.pcicr
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#define PCIE0 0
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#define PCIE1 1
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#define PCIE2 2
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//serial channel
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#define UCSR0A io.ucsr0[SIM_A]
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#define UCSR0B io.ucsr0[SIM_B]
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#define UDR0 io.udr[0]
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#define UDRIE0 0
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#define RXCIE0 1
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#define RXEN0 2
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#define TXEN0 3
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#define U2X0 4
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#define UBRR0H io.ubrr0.h
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#define UBRR0L io.ubrr0.l
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#define PCMSK0 io.pcmsk[0]
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#define PCMSK1 io.pcmsk[1]
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#define PCMSK2 io.pcmsk[2]
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//GPIO
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#define GPIOR0 io.gpior[0]
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#define GPIOR1 io.gpior[1]
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#define GPIOR2 io.gpior[2]
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//MCU Status
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#define MCUSR io.mcusr
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#define PORF 0
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#define EXTRF 1
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#define BORF 2
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#define WDRF 3
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#define JTRF 4
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//Interrupt Status
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#define SREG io.sreg
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#endif
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