Made CPU-MAP per Board instead of MCU
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@ -31,13 +31,14 @@
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#include "LPC17xx.h"
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#include "LPC17xx.h"
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// Define CPU pin map and default settings.
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// Define board type for pin map and default settings.
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// NOTE: OEMs can avoid the need to maintain/update the defaults.h and cpu_map.h files and use only
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//#define CPU_MAP_SMOOTHIEBOARD // Smoothieboard (NXP LPC1769 MCU)
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// one configuration file by placing their specific defaults and pin map at the bottom of this file.
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#define CPU_MAP_C3D_REMIX // Cohesion3D Remix (NXP LPC1769 MCU)
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// If doing so, simply comment out these two defines and see instructions below.
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//#define CPU_MAP_C3D_MINI // Cohesion3D Mini (NXP LPC1769 MCU)
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#define CPU_MAP_LPC1769 // NXP LPC1769 boards (like Smoothieboard, Cohesion3D, MKS SBase)
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//#define CPU_MAP_MKS_SBASE // MKS SBASE Board (NXP LPC1768 MCU)
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#define BOARD_C3D // For boards without i2c stepper current chip (like Cohesion3D).
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//#define CPU_MAP_AZTEEG_X5 // Azteeg X5 boards with NXP LPC1769 mcu
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// Define machine type for machine specific defaults
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//#define DEFAULTS_GENERIC
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//#define DEFAULTS_GENERIC
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#define DEFAULTS_K40
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#define DEFAULTS_K40
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//#define DEFAULTS_FABKIT
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//#define DEFAULTS_FABKIT
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@ -135,7 +136,7 @@
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// #define HOMING_FORCE_SET_ORIGIN // Uncomment to enable.
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// #define HOMING_FORCE_SET_ORIGIN // Uncomment to enable.
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// Uncomment this define to force Grbl to always set the machine origin at bottom left.
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// Uncomment this define to force Grbl to always set the machine origin at bottom left.
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#define HOMING_FORCE_POSITIVE_SPACE // Uncomment to enable.
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//#define HOMING_FORCE_POSITIVE_SPACE // Uncomment to enable.
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// Number of blocks Grbl executes upon startup. These blocks are stored in EEPROM, where the size
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// Number of blocks Grbl executes upon startup. These blocks are stored in EEPROM, where the size
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// and addresses are defined in settings.h. With the current settings, up to 2 startup blocks may
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// and addresses are defined in settings.h. With the current settings, up to 2 startup blocks may
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471
grbl/cpu_map.h
471
grbl/cpu_map.h
@ -150,7 +150,7 @@
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#endif
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#endif
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#ifdef CPU_MAP_LPC1769 // (Boards with NXP-LPC1769 MCU, like Smoothieboard, Cohesion3D, MKS SBase) Only supported by grbl_LPC
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#ifdef CPU_MAP_SMOOTHIEBOARD // (Smoothieboards)
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// Define serial port pins and interrupt vectors.
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// Define serial port pins and interrupt vectors.
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#define SERIAL_RX USART_RX_vect
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#define SERIAL_RX USART_RX_vect
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@ -195,37 +195,12 @@
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#define LIMIT_PIN LPC_GPIO1->FIOPIN
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#define LIMIT_PIN LPC_GPIO1->FIOPIN
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#define LIMIT_PORT LPC_GPIO1->FIOPIN
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#define LIMIT_PORT LPC_GPIO1->FIOPIN
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#define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=25
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#define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=25
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#define Y_LIMIT_BIT 27 // Y-MIN=26, Y-MAX=27
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#define Y_LIMIT_BIT 26 // Y-MIN=26, Y-MAX=27
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#define Z_LIMIT_BIT 29 // Z-MIN=28, Z-MAX=29
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#define Z_LIMIT_BIT 29 // Z-MIN=28, Z-MAX=29
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#define A_LIMIT_BIT 28 // reuse p1.28, as z-min is not often used
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#define A_LIMIT_BIT 28 // reuse p1.28, as z-min is not often used
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//#define B_LIMIT_BIT NotUsed
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//#define B_LIMIT_BIT NotUsed
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//#define C_LIMIT_BIT NotUsed
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//#define C_LIMIT_BIT NotUsed
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#define LIMIT_MASK ((1<<X_LIMIT_BIT)|(1<<Y_LIMIT_BIT)|(1<<Z_LIMIT_BIT)|(1<<A_LIMIT_BIT)) // All limit bits
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#define LIMIT_MASK ((1<<X_LIMIT_BIT)|(1<<Y_LIMIT_BIT)|(1<<Z_LIMIT_BIT)|(1<<A_LIMIT_BIT)) // All limit bits
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// hard limits not ported #define LIMIT_INT PCIE0 // Pin change interrupt enable pin
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// hard limits not ported #define LIMIT_INT_vect PCINT0_vect
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// hard limits not ported #define LIMIT_PCMSK PCMSK0 // Pin change interrupt register
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// Define spindle enable and spindle direction output pins.
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/* not ported
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#define SPINDLE_ENABLE_DDR DDRB
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#define SPINDLE_ENABLE_PORT PORTB
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// Z Limit pin and spindle PWM/enable pin swapped to access hardware PWM on Pin 11.
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#ifdef VARIABLE_SPINDLE
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#ifdef USE_SPINDLE_DIR_AS_ENABLE_PIN
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// If enabled, spindle direction pin now used as spindle enable, while PWM remains on D11.
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#define SPINDLE_ENABLE_BIT 5 // Uno Digital Pin 13 (NOTE: D13 can't be pulled-high input due to LED.)
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#else
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#define SPINDLE_ENABLE_BIT 3 // Uno Digital Pin 11
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#endif
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#else
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#define SPINDLE_ENABLE_BIT 4 // Uno Digital Pin 12
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#endif
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#ifndef USE_SPINDLE_DIR_AS_ENABLE_PIN
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#define SPINDLE_DIRECTION_DDR DDRB
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#define SPINDLE_DIRECTION_PORT PORTB
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#define SPINDLE_DIRECTION_BIT 5 // Uno Digital Pin 13 (NOTE: D13 can't be pulled-high input due to LED.)
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#endif
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*/
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// Define flood and mist coolant enable output pins.
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// Define flood and mist coolant enable output pins.
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#define COOLANT_FLOOD_DDR NotUsed
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#define COOLANT_FLOOD_DDR NotUsed
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@ -267,12 +242,10 @@
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#define SPINDLE_PWM_USE_SECONDARY_PIN true
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#define SPINDLE_PWM_USE_SECONDARY_PIN true
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// Stepper current control
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// Stepper current control
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#ifndef BOARD_C3D
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#define CURRENT_I2C Driver_I2C1 // I2C driver for current control. Comment out to disable (for C3d boards!)
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#define CURRENT_I2C Driver_I2C1 // I2C driver for current control. Comment out to disable (for C3d boards!)
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#define CURRENT_MCP44XX_ADDR 0b0101100 // Address of MCP44XX
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#define CURRENT_MCP44XX_ADDR 0b0101100 // Address of MCP44XX
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#define CURRENT_WIPERS {0, 1, 6, 7}; // Wiper registers (X, Y, Z, A)
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#define CURRENT_WIPERS {0, 1, 6, 7}; // Wiper registers (X, Y, Z, A)
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#define CURRENT_FACTOR 113.33 // Convert amps to digipot value
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#define CURRENT_FACTOR 113.33 // Convert amps to digipot value
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#endif
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// Variable spindle configuration below. Do not change unless you know what you are doing.
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// Variable spindle configuration below. Do not change unless you know what you are doing.
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// NOTE: Only used when variable spindle is enabled.
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// NOTE: Only used when variable spindle is enabled.
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@ -286,23 +259,433 @@
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#define SPINDLE_TCCRB_REGISTER TCCR2B
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#define SPINDLE_TCCRB_REGISTER TCCR2B
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#define SPINDLE_OCR_REGISTER OCR2A
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#define SPINDLE_OCR_REGISTER OCR2A
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#define SPINDLE_COMB_BIT COM2A1
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#define SPINDLE_COMB_BIT COM2A1
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// Prescaled, 8-bit Fast PWM mode.
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/* not used
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#define SPINDLE_TCCRA_INIT_MASK ((1<<WGM20) | (1<<WGM21)) // Configures fast PWM mode.
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// #define SPINDLE_TCCRB_INIT_MASK (1<<CS20) // Disable prescaler -> 62.5kHz
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// #define SPINDLE_TCCRB_INIT_MASK (1<<CS21) // 1/8 prescaler -> 7.8kHz (Used in v0.9)
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// #define SPINDLE_TCCRB_INIT_MASK ((1<<CS21) | (1<<CS20)) // 1/32 prescaler -> 1.96kHz
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#define SPINDLE_TCCRB_INIT_MASK (1<<CS22) // 1/64 prescaler -> 0.98kHz (J-tech laser)
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// NOTE: On the 328p, these must be the same as the SPINDLE_ENABLE settings.
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#define SPINDLE_PWM_DDR DDRB
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#define SPINDLE_PWM_PORT PORTB
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#define SPINDLE_PWM_BIT 3 // Uno Digital Pin 11
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*/
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#endif
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#endif
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#ifdef CPU_MAP_C3D_REMIX // (Cohesion3D Remix Boards)
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// Define serial port pins and interrupt vectors.
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#define SERIAL_RX USART_RX_vect
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#define SERIAL_UDRE USART_UDRE_vect
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// Define step pulse output pins. NOTE: All step bit pins must be on the same port.
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#define STEP_DDR LPC_GPIO2->FIODIR
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#define STEP_PORT LPC_GPIO2->FIOPIN
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#define X_STEP_BIT 0
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#define Y_STEP_BIT 1
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#define Z_STEP_BIT 2
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#define A_STEP_BIT 3
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//#define B_STEP_BIT 8
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//#define C_STEP_BIT 9
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#define STEP_MASK ((1<<X_STEP_BIT)|(1<<Y_STEP_BIT)|(1<<Z_STEP_BIT)|(1<<A_STEP_BIT)) // All step bits
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// Define step direction output pins. NOTE: All direction pins must be on the same port.
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#define DIRECTION_DDR LPC_GPIO0->FIODIR
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#define DIRECTION_PORT LPC_GPIO0->FIOPIN
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#define X_DIRECTION_BIT 5
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#define Y_DIRECTION_BIT 11
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#define Z_DIRECTION_BIT 20
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#define A_DIRECTION_BIT 22
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//#define B_DIRECTION_BIT 13
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//#define C_DIRECTION_BIT NotUsed
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#define DIRECTION_MASK ((1<<X_DIRECTION_BIT)|(1<<Y_DIRECTION_BIT)|(1<<Z_DIRECTION_BIT)|(1<<A_DIRECTION_BIT)) // All direction bits
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// Define stepper driver enable/disable output pin.
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#define STEPPERS_DISABLE_DDR LPC_GPIO0->FIODIR
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#define STEPPERS_DISABLE_PORT LPC_GPIO0->FIOPIN
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#define X_DISABLE_BIT 4
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#define Y_DISABLE_BIT 10
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#define Z_DISABLE_BIT 19
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#define A_DISABLE_BIT 21
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//#define B_DISABLE_BIT 29
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//#define C_DISABLE_BIT NotUsed
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#define STEPPERS_DISABLE_MASK ((1<<X_DISABLE_BIT)|(1<<Y_DISABLE_BIT)|(1<<Z_DISABLE_BIT)|(1<<A_DISABLE_BIT))
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// Define homing/hard limit switch input pins and limit interrupt vectors.
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// NOTE: All limit bit pins must be on the same port, but not on a port with other input pins (CONTROL).
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#define LIMIT_DDR LPC_GPIO1->FIODIR
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#define LIMIT_PIN LPC_GPIO1->FIOPIN
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#define LIMIT_PORT LPC_GPIO1->FIOPIN
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#define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=25
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#define Y_LIMIT_BIT 26 // Y-MIN=26, Y-MAX=27
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#define Z_LIMIT_BIT 28 // Z-MIN=28, Z-MAX=29
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#define A_LIMIT_BIT 29 // reuse p1.25 from Z-MAX
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//#define B_LIMIT_BIT NotUsed
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//#define C_LIMIT_BIT NotUsed
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#define LIMIT_MASK ((1<<X_LIMIT_BIT)|(1<<Y_LIMIT_BIT)|(1<<Z_LIMIT_BIT)|(1<<A_LIMIT_BIT)) // All limit bits
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// Define flood and mist coolant enable output pins.
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#define COOLANT_FLOOD_DDR NotUsed
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#define COOLANT_FLOOD_PORT NotUsed
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#define COOLANT_FLOOD_BIT 3 // Uno Analog Pin 3
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#define COOLANT_MIST_DDR NotUsed
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#define COOLANT_MIST_PORT NotUsed
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#define COOLANT_MIST_BIT 4 // Uno Analog Pin 3
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// Define user-control controls (cycle start, reset, feed hold) input pins.
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// NOTE: All CONTROLs pins must be on the same port and not on a port with other input pins (limits).
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#define CONTROL_DDR NotUsed
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#define CONTROL_PIN NotUsed
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#define CONTROL_PORT NotUsed
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#define CONTROL_RESET_BIT 0 // Uno Analog Pin 0
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#define CONTROL_FEED_HOLD_BIT 1 // Uno Analog Pin 1
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#define CONTROL_CYCLE_START_BIT 2 // Uno Analog Pin 2
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#define CONTROL_SAFETY_DOOR_BIT 1 // Uno Analog Pin 1 NOTE: Safety door is shared with feed hold. Enabled by config define.
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#define CONTROL_INT PCIE1 // Pin change interrupt enable pin
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#define CONTROL_INT_vect PCINT1_vect
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#define CONTROL_PCMSK NotUsed // Pin change interrupt register
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#define CONTROL_MASK ((1<<CONTROL_RESET_BIT)|(1<<CONTROL_FEED_HOLD_BIT)|(1<<CONTROL_CYCLE_START_BIT)|(1<<CONTROL_SAFETY_DOOR_BIT))
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#define CONTROL_INVERT_MASK CONTROL_MASK // May be re-defined to only invert certain control pins.
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// Define probe switch input pin.
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#define PROBE_DDR NotUsed
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#define PROBE_PIN NotUsed
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#define PROBE_PORT NotUsed
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#define PROBE_BIT 5 // Uno Analog Pin 5
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#define PROBE_MASK (1<<PROBE_BIT)
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// The LPC17xx has 6 PWM channels. Each channel has 2 pins. It can drive both pins simultaneously to the same value.
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//
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// PWM Channel PWM1_CH1 PWM1_CH2 PWM1_CH3 PWM1_CH4 PWM1_CH5 PWM1_CH6
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// Primary pin P1.18 P1.20 P1.21 P1.23 P1.24 P1.26
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// Secondary pin P2.0 P2.1 P2.2 P2.3 P2.4 P2.5
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#define SPINDLE_PWM_CHANNEL PWM1_CH6
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#define SPINDLE_PWM_USE_PRIMARY_PIN false
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#define SPINDLE_PWM_USE_SECONDARY_PIN true
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// Variable spindle configuration below. Do not change unless you know what you are doing.
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// NOTE: Only used when variable spindle is enabled.
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#define SPINDLE_PWM_MAX_VALUE 255 // Don't change. 328p fast PWM mode fixes top value as 255.
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#ifndef SPINDLE_PWM_MIN_VALUE
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#define SPINDLE_PWM_MIN_VALUE 1 // Must be greater than zero.
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#endif
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//#define SPINDLE_PWM_OFF_VALUE 0 // Defined in config.h
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#define SPINDLE_PWM_RANGE (SPINDLE_PWM_MAX_VALUE-SPINDLE_PWM_MIN_VALUE)
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#define SPINDLE_TCCRA_REGISTER TCCR2A
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#define SPINDLE_TCCRB_REGISTER TCCR2B
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#define SPINDLE_OCR_REGISTER OCR2A
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#define SPINDLE_COMB_BIT COM2A1
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#endif
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#ifdef CPU_MAP_C3D_MINI // (Cohesion3D Mini Boards)
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// Define serial port pins and interrupt vectors.
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#define SERIAL_RX USART_RX_vect
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#define SERIAL_UDRE USART_UDRE_vect
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// Define step pulse output pins. NOTE: All step bit pins must be on the same port.
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#define STEP_DDR LPC_GPIO2->FIODIR
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#define STEP_PORT LPC_GPIO2->FIOPIN
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#define X_STEP_BIT 0
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#define Y_STEP_BIT 1
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#define Z_STEP_BIT 2
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#define A_STEP_BIT 3
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//#define B_STEP_BIT 8
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//#define C_STEP_BIT 9
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#define STEP_MASK ((1<<X_STEP_BIT)|(1<<Y_STEP_BIT)|(1<<Z_STEP_BIT)|(1<<A_STEP_BIT)) // All step bits
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// Define step direction output pins. NOTE: All direction pins must be on the same port.
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#define DIRECTION_DDR LPC_GPIO0->FIODIR
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#define DIRECTION_PORT LPC_GPIO0->FIOPIN
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#define X_DIRECTION_BIT 5
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#define Y_DIRECTION_BIT 11
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#define Z_DIRECTION_BIT 20
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#define A_DIRECTION_BIT 22
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//#define B_DIRECTION_BIT 13
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//#define C_DIRECTION_BIT NotUsed
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#define DIRECTION_MASK ((1<<X_DIRECTION_BIT)|(1<<Y_DIRECTION_BIT)|(1<<Z_DIRECTION_BIT)|(1<<A_DIRECTION_BIT)) // All direction bits
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// Define stepper driver enable/disable output pin.
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#define STEPPERS_DISABLE_DDR LPC_GPIO0->FIODIR
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#define STEPPERS_DISABLE_PORT LPC_GPIO0->FIOPIN
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#define X_DISABLE_BIT 4
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#define Y_DISABLE_BIT 10
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#define Z_DISABLE_BIT 19
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#define A_DISABLE_BIT 21
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//#define B_DISABLE_BIT 29
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//#define C_DISABLE_BIT NotUsed
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#define STEPPERS_DISABLE_MASK ((1<<X_DISABLE_BIT)|(1<<Y_DISABLE_BIT)|(1<<Z_DISABLE_BIT)|(1<<A_DISABLE_BIT))
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// Define homing/hard limit switch input pins and limit interrupt vectors.
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// NOTE: All limit bit pins must be on the same port, but not on a port with other input pins (CONTROL).
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#define LIMIT_DDR LPC_GPIO1->FIODIR
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#define LIMIT_PIN LPC_GPIO1->FIOPIN
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#define LIMIT_PORT LPC_GPIO1->FIOPIN
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#define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=25
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#define Y_LIMIT_BIT 26 // Y-MIN=26, Y-MAX=27
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#define Z_LIMIT_BIT 28 // Z-MIN=28, Z-MAX=29
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#define A_LIMIT_BIT 29 // reuse p1.29 from Z-MAX
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//#define B_LIMIT_BIT NotUsed
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//#define C_LIMIT_BIT NotUsed
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#define LIMIT_MASK ((1<<X_LIMIT_BIT)|(1<<Y_LIMIT_BIT)|(1<<Z_LIMIT_BIT)|(1<<A_LIMIT_BIT)) // All limit bits
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// Define flood and mist coolant enable output pins.
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#define COOLANT_FLOOD_DDR NotUsed
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#define COOLANT_FLOOD_PORT NotUsed
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#define COOLANT_FLOOD_BIT 3 // Uno Analog Pin 3
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#define COOLANT_MIST_DDR NotUsed
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||||||
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#define COOLANT_MIST_PORT NotUsed
|
||||||
|
#define COOLANT_MIST_BIT 4 // Uno Analog Pin 3
|
||||||
|
|
||||||
|
// Define user-control controls (cycle start, reset, feed hold) input pins.
|
||||||
|
// NOTE: All CONTROLs pins must be on the same port and not on a port with other input pins (limits).
|
||||||
|
#define CONTROL_DDR NotUsed
|
||||||
|
#define CONTROL_PIN NotUsed
|
||||||
|
#define CONTROL_PORT NotUsed
|
||||||
|
#define CONTROL_RESET_BIT 0 // Uno Analog Pin 0
|
||||||
|
#define CONTROL_FEED_HOLD_BIT 1 // Uno Analog Pin 1
|
||||||
|
#define CONTROL_CYCLE_START_BIT 2 // Uno Analog Pin 2
|
||||||
|
#define CONTROL_SAFETY_DOOR_BIT 1 // Uno Analog Pin 1 NOTE: Safety door is shared with feed hold. Enabled by config define.
|
||||||
|
#define CONTROL_INT PCIE1 // Pin change interrupt enable pin
|
||||||
|
#define CONTROL_INT_vect PCINT1_vect
|
||||||
|
#define CONTROL_PCMSK NotUsed // Pin change interrupt register
|
||||||
|
#define CONTROL_MASK ((1<<CONTROL_RESET_BIT)|(1<<CONTROL_FEED_HOLD_BIT)|(1<<CONTROL_CYCLE_START_BIT)|(1<<CONTROL_SAFETY_DOOR_BIT))
|
||||||
|
#define CONTROL_INVERT_MASK CONTROL_MASK // May be re-defined to only invert certain control pins.
|
||||||
|
|
||||||
|
// Define probe switch input pin.
|
||||||
|
#define PROBE_DDR NotUsed
|
||||||
|
#define PROBE_PIN NotUsed
|
||||||
|
#define PROBE_PORT NotUsed
|
||||||
|
#define PROBE_BIT 5 // Uno Analog Pin 5
|
||||||
|
#define PROBE_MASK (1<<PROBE_BIT)
|
||||||
|
|
||||||
|
// The LPC17xx has 6 PWM channels. Each channel has 2 pins. It can drive both pins simultaneously to the same value.
|
||||||
|
//
|
||||||
|
// PWM Channel PWM1_CH1 PWM1_CH2 PWM1_CH3 PWM1_CH4 PWM1_CH5 PWM1_CH6
|
||||||
|
// Primary pin P1.18 P1.20 P1.21 P1.23 P1.24 P1.26
|
||||||
|
// Secondary pin P2.0 P2.1 P2.2 P2.3 P2.4 P2.5
|
||||||
|
#define SPINDLE_PWM_CHANNEL PWM1_CH6
|
||||||
|
#define SPINDLE_PWM_USE_PRIMARY_PIN false
|
||||||
|
#define SPINDLE_PWM_USE_SECONDARY_PIN true
|
||||||
|
|
||||||
|
// Variable spindle configuration below. Do not change unless you know what you are doing.
|
||||||
|
// NOTE: Only used when variable spindle is enabled.
|
||||||
|
#define SPINDLE_PWM_MAX_VALUE 255 // Don't change. 328p fast PWM mode fixes top value as 255.
|
||||||
|
#ifndef SPINDLE_PWM_MIN_VALUE
|
||||||
|
#define SPINDLE_PWM_MIN_VALUE 1 // Must be greater than zero.
|
||||||
|
#endif
|
||||||
|
//#define SPINDLE_PWM_OFF_VALUE 0 // Defined in config.h
|
||||||
|
#define SPINDLE_PWM_RANGE (SPINDLE_PWM_MAX_VALUE-SPINDLE_PWM_MIN_VALUE)
|
||||||
|
#define SPINDLE_TCCRA_REGISTER TCCR2A
|
||||||
|
#define SPINDLE_TCCRB_REGISTER TCCR2B
|
||||||
|
#define SPINDLE_OCR_REGISTER OCR2A
|
||||||
|
#define SPINDLE_COMB_BIT COM2A1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef CPU_MAP_MKS_SBASE // (MKS SBASE Boards)
|
||||||
|
|
||||||
|
// Define serial port pins and interrupt vectors.
|
||||||
|
#define SERIAL_RX USART_RX_vect
|
||||||
|
#define SERIAL_UDRE USART_UDRE_vect
|
||||||
|
|
||||||
|
// Define step pulse output pins. NOTE: All step bit pins must be on the same port.
|
||||||
|
#define STEP_DDR LPC_GPIO2->FIODIR
|
||||||
|
#define STEP_PORT LPC_GPIO2->FIOPIN
|
||||||
|
#define X_STEP_BIT 0
|
||||||
|
#define Y_STEP_BIT 1
|
||||||
|
#define Z_STEP_BIT 2
|
||||||
|
#define A_STEP_BIT 3
|
||||||
|
//#define B_STEP_BIT 8
|
||||||
|
//#define C_STEP_BIT 9
|
||||||
|
#define STEP_MASK ((1<<X_STEP_BIT)|(1<<Y_STEP_BIT)|(1<<Z_STEP_BIT)|(1<<A_STEP_BIT)) // All step bits
|
||||||
|
|
||||||
|
// Define step direction output pins. NOTE: All direction pins must be on the same port.
|
||||||
|
#define DIRECTION_DDR LPC_GPIO0->FIODIR
|
||||||
|
#define DIRECTION_PORT LPC_GPIO0->FIOPIN
|
||||||
|
#define X_DIRECTION_BIT 5
|
||||||
|
#define Y_DIRECTION_BIT 11
|
||||||
|
#define Z_DIRECTION_BIT 20
|
||||||
|
#define A_DIRECTION_BIT 22
|
||||||
|
//#define B_DIRECTION_BIT 13
|
||||||
|
//#define C_DIRECTION_BIT NotUsed
|
||||||
|
#define DIRECTION_MASK ((1<<X_DIRECTION_BIT)|(1<<Y_DIRECTION_BIT)|(1<<Z_DIRECTION_BIT)|(1<<A_DIRECTION_BIT)) // All direction bits
|
||||||
|
|
||||||
|
// Define stepper driver enable/disable output pin.
|
||||||
|
#define STEPPERS_DISABLE_DDR LPC_GPIO0->FIODIR
|
||||||
|
#define STEPPERS_DISABLE_PORT LPC_GPIO0->FIOPIN
|
||||||
|
#define X_DISABLE_BIT 4
|
||||||
|
#define Y_DISABLE_BIT 10
|
||||||
|
#define Z_DISABLE_BIT 19
|
||||||
|
#define A_DISABLE_BIT 21
|
||||||
|
//#define B_DISABLE_BIT 29
|
||||||
|
//#define C_DISABLE_BIT NotUsed
|
||||||
|
#define STEPPERS_DISABLE_MASK ((1<<X_DISABLE_BIT)|(1<<Y_DISABLE_BIT)|(1<<Z_DISABLE_BIT)|(1<<A_DISABLE_BIT))
|
||||||
|
|
||||||
|
// Define homing/hard limit switch input pins and limit interrupt vectors.
|
||||||
|
// NOTE: All limit bit pins must be on the same port, but not on a port with other input pins (CONTROL).
|
||||||
|
#define LIMIT_DDR LPC_GPIO1->FIODIR
|
||||||
|
#define LIMIT_PIN LPC_GPIO1->FIOPIN
|
||||||
|
#define LIMIT_PORT LPC_GPIO1->FIOPIN
|
||||||
|
#define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=25
|
||||||
|
#define Y_LIMIT_BIT 26 // Y-MIN=26, Y-MAX=27
|
||||||
|
#define Z_LIMIT_BIT 29 // Z-MIN=28, Z-MAX=29
|
||||||
|
#define A_LIMIT_BIT 28 // reuse p1.28, as z-min is not often used
|
||||||
|
//#define B_LIMIT_BIT NotUsed
|
||||||
|
//#define C_LIMIT_BIT NotUsed
|
||||||
|
#define LIMIT_MASK ((1<<X_LIMIT_BIT)|(1<<Y_LIMIT_BIT)|(1<<Z_LIMIT_BIT)|(1<<A_LIMIT_BIT)) // All limit bits
|
||||||
|
|
||||||
|
// Define flood and mist coolant enable output pins.
|
||||||
|
#define COOLANT_FLOOD_DDR NotUsed
|
||||||
|
#define COOLANT_FLOOD_PORT NotUsed
|
||||||
|
#define COOLANT_FLOOD_BIT 3 // Uno Analog Pin 3
|
||||||
|
#define COOLANT_MIST_DDR NotUsed
|
||||||
|
#define COOLANT_MIST_PORT NotUsed
|
||||||
|
#define COOLANT_MIST_BIT 4 // Uno Analog Pin 3
|
||||||
|
|
||||||
|
// Define user-control controls (cycle start, reset, feed hold) input pins.
|
||||||
|
// NOTE: All CONTROLs pins must be on the same port and not on a port with other input pins (limits).
|
||||||
|
#define CONTROL_DDR NotUsed
|
||||||
|
#define CONTROL_PIN NotUsed
|
||||||
|
#define CONTROL_PORT NotUsed
|
||||||
|
#define CONTROL_RESET_BIT 0 // Uno Analog Pin 0
|
||||||
|
#define CONTROL_FEED_HOLD_BIT 1 // Uno Analog Pin 1
|
||||||
|
#define CONTROL_CYCLE_START_BIT 2 // Uno Analog Pin 2
|
||||||
|
#define CONTROL_SAFETY_DOOR_BIT 1 // Uno Analog Pin 1 NOTE: Safety door is shared with feed hold. Enabled by config define.
|
||||||
|
#define CONTROL_INT PCIE1 // Pin change interrupt enable pin
|
||||||
|
#define CONTROL_INT_vect PCINT1_vect
|
||||||
|
#define CONTROL_PCMSK NotUsed // Pin change interrupt register
|
||||||
|
#define CONTROL_MASK ((1<<CONTROL_RESET_BIT)|(1<<CONTROL_FEED_HOLD_BIT)|(1<<CONTROL_CYCLE_START_BIT)|(1<<CONTROL_SAFETY_DOOR_BIT))
|
||||||
|
#define CONTROL_INVERT_MASK CONTROL_MASK // May be re-defined to only invert certain control pins.
|
||||||
|
|
||||||
|
// Define probe switch input pin.
|
||||||
|
#define PROBE_DDR NotUsed
|
||||||
|
#define PROBE_PIN NotUsed
|
||||||
|
#define PROBE_PORT NotUsed
|
||||||
|
#define PROBE_BIT 5 // Uno Analog Pin 5
|
||||||
|
#define PROBE_MASK (1<<PROBE_BIT)
|
||||||
|
|
||||||
|
// The LPC17xx has 6 PWM channels. Each channel has 2 pins. It can drive both pins simultaneously to the same value.
|
||||||
|
//
|
||||||
|
// PWM Channel PWM1_CH1 PWM1_CH2 PWM1_CH3 PWM1_CH4 PWM1_CH5 PWM1_CH6
|
||||||
|
// Primary pin P1.18 P1.20 P1.21 P1.23 P1.24 P1.26
|
||||||
|
// Secondary pin P2.0 P2.1 P2.2 P2.3 P2.4 P2.5
|
||||||
|
#define SPINDLE_PWM_CHANNEL PWM1_CH6
|
||||||
|
#define SPINDLE_PWM_USE_PRIMARY_PIN false
|
||||||
|
#define SPINDLE_PWM_USE_SECONDARY_PIN true
|
||||||
|
|
||||||
|
// Stepper current control
|
||||||
|
#define CURRENT_I2C Driver_I2C1 // I2C driver for current control. Comment out to disable (for C3d boards!)
|
||||||
|
#define CURRENT_MCP44XX_ADDR 0b0101100 // Address of MCP44XX
|
||||||
|
#define CURRENT_WIPERS {0, 1, 6, 7}; // Wiper registers (X, Y, Z, A)
|
||||||
|
#define CURRENT_FACTOR 113.33 // Convert amps to digipot value
|
||||||
|
|
||||||
|
// Variable spindle configuration below. Do not change unless you know what you are doing.
|
||||||
|
// NOTE: Only used when variable spindle is enabled.
|
||||||
|
#define SPINDLE_PWM_MAX_VALUE 255 // Don't change. 328p fast PWM mode fixes top value as 255.
|
||||||
|
#ifndef SPINDLE_PWM_MIN_VALUE
|
||||||
|
#define SPINDLE_PWM_MIN_VALUE 1 // Must be greater than zero.
|
||||||
|
#endif
|
||||||
|
//#define SPINDLE_PWM_OFF_VALUE 0 // Defined in config.h
|
||||||
|
#define SPINDLE_PWM_RANGE (SPINDLE_PWM_MAX_VALUE-SPINDLE_PWM_MIN_VALUE)
|
||||||
|
#define SPINDLE_TCCRA_REGISTER TCCR2A
|
||||||
|
#define SPINDLE_TCCRB_REGISTER TCCR2B
|
||||||
|
#define SPINDLE_OCR_REGISTER OCR2A
|
||||||
|
#define SPINDLE_COMB_BIT COM2A1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef CPU_MAP_AZTEEG_X5 // (Azteeg X5 Boards) not tested yet!
|
||||||
|
|
||||||
|
// Define serial port pins and interrupt vectors.
|
||||||
|
#define SERIAL_RX USART_RX_vect
|
||||||
|
#define SERIAL_UDRE USART_UDRE_vect
|
||||||
|
|
||||||
|
// Define step pulse output pins. NOTE: All step bit pins must be on the same port.
|
||||||
|
#define STEP_DDR LPC_GPIO2->FIODIR
|
||||||
|
#define STEP_PORT LPC_GPIO2->FIOPIN
|
||||||
|
#define X_STEP_BIT 1
|
||||||
|
#define Y_STEP_BIT 2
|
||||||
|
#define Z_STEP_BIT 3
|
||||||
|
#define A_STEP_BIT 0
|
||||||
|
#define STEP_MASK ((1<<X_STEP_BIT)|(1<<Y_STEP_BIT)|(1<<Z_STEP_BIT)|(1<<A_STEP_BIT)) // All step bits
|
||||||
|
|
||||||
|
// Define step direction output pins. NOTE: All direction pins must be on the same port.
|
||||||
|
#define DIRECTION_DDR LPC_GPIO0->FIODIR
|
||||||
|
#define DIRECTION_PORT LPC_GPIO0->FIOPIN
|
||||||
|
#define X_DIRECTION_BIT 11
|
||||||
|
#define Y_DIRECTION_BIT 20
|
||||||
|
#define Z_DIRECTION_BIT 22
|
||||||
|
#define A_DIRECTION_BIT 5
|
||||||
|
#define DIRECTION_MASK ((1<<X_DIRECTION_BIT)|(1<<Y_DIRECTION_BIT)|(1<<Z_DIRECTION_BIT)|(1<<A_DIRECTION_BIT)) // All direction bits
|
||||||
|
|
||||||
|
// Define stepper driver enable/disable output pin.
|
||||||
|
#define STEPPERS_DISABLE_DDR LPC_GPIO0->FIODIR
|
||||||
|
#define STEPPERS_DISABLE_PORT LPC_GPIO0->FIOPIN
|
||||||
|
#define X_DISABLE_BIT 10
|
||||||
|
#define Y_DISABLE_BIT 19
|
||||||
|
#define Z_DISABLE_BIT 21
|
||||||
|
#define A_DISABLE_BIT 4
|
||||||
|
#define STEPPERS_DISABLE_MASK ((1<<X_DISABLE_BIT)|(1<<Y_DISABLE_BIT)|(1<<Z_DISABLE_BIT)|(1<<A_DISABLE_BIT))
|
||||||
|
|
||||||
|
// Define homing/hard limit switch input pins and limit interrupt vectors.
|
||||||
|
// NOTE: All limit bit pins must be on the same port, but not on a port with other input pins (CONTROL).
|
||||||
|
#define LIMIT_DDR LPC_GPIO1->FIODIR
|
||||||
|
#define LIMIT_PIN LPC_GPIO1->FIOPIN
|
||||||
|
#define LIMIT_PORT LPC_GPIO1->FIOPIN
|
||||||
|
#define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=27
|
||||||
|
#define Y_LIMIT_BIT 25 // Y-MIN=25, Y-MAX=28
|
||||||
|
#define Z_LIMIT_BIT 26 // Z-MIN=26, Z-MAX=29
|
||||||
|
#define A_LIMIT_BIT 27 // reuse p1.27, as X-MAX is not used
|
||||||
|
#define LIMIT_MASK ((1<<X_LIMIT_BIT)|(1<<Y_LIMIT_BIT)|(1<<Z_LIMIT_BIT)|(1<<A_LIMIT_BIT)) // All limit bits
|
||||||
|
|
||||||
|
// Define flood and mist coolant enable output pins.
|
||||||
|
#define COOLANT_FLOOD_DDR NotUsed
|
||||||
|
#define COOLANT_FLOOD_PORT NotUsed
|
||||||
|
#define COOLANT_FLOOD_BIT 3 // Uno Analog Pin 3
|
||||||
|
#define COOLANT_MIST_DDR NotUsed
|
||||||
|
#define COOLANT_MIST_PORT NotUsed
|
||||||
|
#define COOLANT_MIST_BIT 4 // Uno Analog Pin 3
|
||||||
|
|
||||||
|
// Define user-control controls (cycle start, reset, feed hold) input pins.
|
||||||
|
// NOTE: All CONTROLs pins must be on the same port and not on a port with other input pins (limits).
|
||||||
|
#define CONTROL_DDR NotUsed
|
||||||
|
#define CONTROL_PIN NotUsed
|
||||||
|
#define CONTROL_PORT NotUsed
|
||||||
|
#define CONTROL_RESET_BIT 0 // Uno Analog Pin 0
|
||||||
|
#define CONTROL_FEED_HOLD_BIT 1 // Uno Analog Pin 1
|
||||||
|
#define CONTROL_CYCLE_START_BIT 2 // Uno Analog Pin 2
|
||||||
|
#define CONTROL_SAFETY_DOOR_BIT 1 // Uno Analog Pin 1 NOTE: Safety door is shared with feed hold. Enabled by config define.
|
||||||
|
#define CONTROL_INT PCIE1 // Pin change interrupt enable pin
|
||||||
|
#define CONTROL_INT_vect PCINT1_vect
|
||||||
|
#define CONTROL_PCMSK NotUsed // Pin change interrupt register
|
||||||
|
#define CONTROL_MASK ((1<<CONTROL_RESET_BIT)|(1<<CONTROL_FEED_HOLD_BIT)|(1<<CONTROL_CYCLE_START_BIT)|(1<<CONTROL_SAFETY_DOOR_BIT))
|
||||||
|
#define CONTROL_INVERT_MASK CONTROL_MASK // May be re-defined to only invert certain control pins.
|
||||||
|
|
||||||
|
// Define probe switch input pin.
|
||||||
|
#define PROBE_DDR NotUsed
|
||||||
|
#define PROBE_PIN NotUsed
|
||||||
|
#define PROBE_PORT NotUsed
|
||||||
|
#define PROBE_BIT 5 // Uno Analog Pin 5
|
||||||
|
#define PROBE_MASK (1<<PROBE_BIT)
|
||||||
|
|
||||||
|
// The LPC17xx has 6 PWM channels. Each channel has 2 pins. It can drive both pins simultaneously to the same value.
|
||||||
|
//
|
||||||
|
// PWM Channel PWM1_CH1 PWM1_CH2 PWM1_CH3 PWM1_CH4 PWM1_CH5 PWM1_CH6 PWM1_CH7 PWM1_CH8
|
||||||
|
// Primary pin P1.18 P1.20 P1.21 P1.23 P1.24 P1.26 ? ?
|
||||||
|
// Secondary pin P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
|
||||||
|
#define SPINDLE_PWM_CHANNEL PWM1_CH8
|
||||||
|
#define SPINDLE_PWM_USE_PRIMARY_PIN false
|
||||||
|
#define SPINDLE_PWM_USE_SECONDARY_PIN true
|
||||||
|
|
||||||
|
// Stepper current control via SPI not ported yet!
|
||||||
|
|
||||||
|
// Variable spindle configuration below. Do not change unless you know what you are doing.
|
||||||
|
// NOTE: Only used when variable spindle is enabled.
|
||||||
|
#define SPINDLE_PWM_MAX_VALUE 255 // Don't change. 328p fast PWM mode fixes top value as 255.
|
||||||
|
#ifndef SPINDLE_PWM_MIN_VALUE
|
||||||
|
#define SPINDLE_PWM_MIN_VALUE 1 // Must be greater than zero.
|
||||||
|
#endif
|
||||||
|
//#define SPINDLE_PWM_OFF_VALUE 0 // Defined in config.h
|
||||||
|
#define SPINDLE_PWM_RANGE (SPINDLE_PWM_MAX_VALUE-SPINDLE_PWM_MIN_VALUE)
|
||||||
|
#define SPINDLE_TCCRA_REGISTER TCCR2A
|
||||||
|
#define SPINDLE_TCCRB_REGISTER TCCR2B
|
||||||
|
#define SPINDLE_OCR_REGISTER OCR2A
|
||||||
|
#define SPINDLE_COMB_BIT COM2A1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
#ifdef CPU_MAP_CUSTOM_PROC
|
#ifdef CPU_MAP_CUSTOM_PROC
|
||||||
// For a custom pin map or different processor, copy and edit one of the available cpu
|
// For a custom pin map or different processor, copy and edit one of the available cpu
|
||||||
|
Loading…
Reference in New Issue
Block a user