diff --git a/grbl/config.h b/grbl/config.h index 8ddb23f..2774542 100644 --- a/grbl/config.h +++ b/grbl/config.h @@ -31,13 +31,14 @@ #include "LPC17xx.h" -// Define CPU pin map and default settings. -// NOTE: OEMs can avoid the need to maintain/update the defaults.h and cpu_map.h files and use only -// one configuration file by placing their specific defaults and pin map at the bottom of this file. -// If doing so, simply comment out these two defines and see instructions below. -#define CPU_MAP_LPC1769 // NXP LPC1769 boards (like Smoothieboard, Cohesion3D, MKS SBase) -#define BOARD_C3D // For boards without i2c stepper current chip (like Cohesion3D). +// Define board type for pin map and default settings. +//#define CPU_MAP_SMOOTHIEBOARD // Smoothieboard (NXP LPC1769 MCU) +#define CPU_MAP_C3D_REMIX // Cohesion3D Remix (NXP LPC1769 MCU) +//#define CPU_MAP_C3D_MINI // Cohesion3D Mini (NXP LPC1769 MCU) +//#define CPU_MAP_MKS_SBASE // MKS SBASE Board (NXP LPC1768 MCU) +//#define CPU_MAP_AZTEEG_X5 // Azteeg X5 boards with NXP LPC1769 mcu +// Define machine type for machine specific defaults //#define DEFAULTS_GENERIC #define DEFAULTS_K40 //#define DEFAULTS_FABKIT @@ -135,7 +136,7 @@ // #define HOMING_FORCE_SET_ORIGIN // Uncomment to enable. // Uncomment this define to force Grbl to always set the machine origin at bottom left. -#define HOMING_FORCE_POSITIVE_SPACE // Uncomment to enable. +//#define HOMING_FORCE_POSITIVE_SPACE // Uncomment to enable. // Number of blocks Grbl executes upon startup. These blocks are stored in EEPROM, where the size // and addresses are defined in settings.h. With the current settings, up to 2 startup blocks may diff --git a/grbl/cpu_map.h b/grbl/cpu_map.h index 3479eea..691c62b 100644 --- a/grbl/cpu_map.h +++ b/grbl/cpu_map.h @@ -150,7 +150,7 @@ #endif -#ifdef CPU_MAP_LPC1769 // (Boards with NXP-LPC1769 MCU, like Smoothieboard, Cohesion3D, MKS SBase) Only supported by grbl_LPC +#ifdef CPU_MAP_SMOOTHIEBOARD // (Smoothieboards) // Define serial port pins and interrupt vectors. #define SERIAL_RX USART_RX_vect @@ -195,37 +195,12 @@ #define LIMIT_PIN LPC_GPIO1->FIOPIN #define LIMIT_PORT LPC_GPIO1->FIOPIN #define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=25 - #define Y_LIMIT_BIT 27 // Y-MIN=26, Y-MAX=27 + #define Y_LIMIT_BIT 26 // Y-MIN=26, Y-MAX=27 #define Z_LIMIT_BIT 29 // Z-MIN=28, Z-MAX=29 #define A_LIMIT_BIT 28 // reuse p1.28, as z-min is not often used //#define B_LIMIT_BIT NotUsed //#define C_LIMIT_BIT NotUsed #define LIMIT_MASK ((1< 62.5kHz - // #define SPINDLE_TCCRB_INIT_MASK (1< 7.8kHz (Used in v0.9) - // #define SPINDLE_TCCRB_INIT_MASK ((1< 1.96kHz - #define SPINDLE_TCCRB_INIT_MASK (1< 0.98kHz (J-tech laser) - - // NOTE: On the 328p, these must be the same as the SPINDLE_ENABLE settings. - #define SPINDLE_PWM_DDR DDRB - #define SPINDLE_PWM_PORT PORTB - #define SPINDLE_PWM_BIT 3 // Uno Digital Pin 11 - */ - #endif + +#ifdef CPU_MAP_C3D_REMIX // (Cohesion3D Remix Boards) + + // Define serial port pins and interrupt vectors. + #define SERIAL_RX USART_RX_vect + #define SERIAL_UDRE USART_UDRE_vect + + // Define step pulse output pins. NOTE: All step bit pins must be on the same port. + #define STEP_DDR LPC_GPIO2->FIODIR + #define STEP_PORT LPC_GPIO2->FIOPIN + #define X_STEP_BIT 0 + #define Y_STEP_BIT 1 + #define Z_STEP_BIT 2 + #define A_STEP_BIT 3 + //#define B_STEP_BIT 8 + //#define C_STEP_BIT 9 + #define STEP_MASK ((1<FIODIR + #define DIRECTION_PORT LPC_GPIO0->FIOPIN + #define X_DIRECTION_BIT 5 + #define Y_DIRECTION_BIT 11 + #define Z_DIRECTION_BIT 20 + #define A_DIRECTION_BIT 22 + //#define B_DIRECTION_BIT 13 + //#define C_DIRECTION_BIT NotUsed + #define DIRECTION_MASK ((1<FIODIR + #define STEPPERS_DISABLE_PORT LPC_GPIO0->FIOPIN + #define X_DISABLE_BIT 4 + #define Y_DISABLE_BIT 10 + #define Z_DISABLE_BIT 19 + #define A_DISABLE_BIT 21 + //#define B_DISABLE_BIT 29 + //#define C_DISABLE_BIT NotUsed + #define STEPPERS_DISABLE_MASK ((1<FIODIR + #define LIMIT_PIN LPC_GPIO1->FIOPIN + #define LIMIT_PORT LPC_GPIO1->FIOPIN + #define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=25 + #define Y_LIMIT_BIT 26 // Y-MIN=26, Y-MAX=27 + #define Z_LIMIT_BIT 28 // Z-MIN=28, Z-MAX=29 + #define A_LIMIT_BIT 29 // reuse p1.25 from Z-MAX + //#define B_LIMIT_BIT NotUsed + //#define C_LIMIT_BIT NotUsed + #define LIMIT_MASK ((1<FIODIR + #define STEP_PORT LPC_GPIO2->FIOPIN + #define X_STEP_BIT 0 + #define Y_STEP_BIT 1 + #define Z_STEP_BIT 2 + #define A_STEP_BIT 3 + //#define B_STEP_BIT 8 + //#define C_STEP_BIT 9 + #define STEP_MASK ((1<FIODIR + #define DIRECTION_PORT LPC_GPIO0->FIOPIN + #define X_DIRECTION_BIT 5 + #define Y_DIRECTION_BIT 11 + #define Z_DIRECTION_BIT 20 + #define A_DIRECTION_BIT 22 + //#define B_DIRECTION_BIT 13 + //#define C_DIRECTION_BIT NotUsed + #define DIRECTION_MASK ((1<FIODIR + #define STEPPERS_DISABLE_PORT LPC_GPIO0->FIOPIN + #define X_DISABLE_BIT 4 + #define Y_DISABLE_BIT 10 + #define Z_DISABLE_BIT 19 + #define A_DISABLE_BIT 21 + //#define B_DISABLE_BIT 29 + //#define C_DISABLE_BIT NotUsed + #define STEPPERS_DISABLE_MASK ((1<FIODIR + #define LIMIT_PIN LPC_GPIO1->FIOPIN + #define LIMIT_PORT LPC_GPIO1->FIOPIN + #define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=25 + #define Y_LIMIT_BIT 26 // Y-MIN=26, Y-MAX=27 + #define Z_LIMIT_BIT 28 // Z-MIN=28, Z-MAX=29 + #define A_LIMIT_BIT 29 // reuse p1.29 from Z-MAX + //#define B_LIMIT_BIT NotUsed + //#define C_LIMIT_BIT NotUsed + #define LIMIT_MASK ((1<FIODIR + #define STEP_PORT LPC_GPIO2->FIOPIN + #define X_STEP_BIT 0 + #define Y_STEP_BIT 1 + #define Z_STEP_BIT 2 + #define A_STEP_BIT 3 + //#define B_STEP_BIT 8 + //#define C_STEP_BIT 9 + #define STEP_MASK ((1<FIODIR + #define DIRECTION_PORT LPC_GPIO0->FIOPIN + #define X_DIRECTION_BIT 5 + #define Y_DIRECTION_BIT 11 + #define Z_DIRECTION_BIT 20 + #define A_DIRECTION_BIT 22 + //#define B_DIRECTION_BIT 13 + //#define C_DIRECTION_BIT NotUsed + #define DIRECTION_MASK ((1<FIODIR + #define STEPPERS_DISABLE_PORT LPC_GPIO0->FIOPIN + #define X_DISABLE_BIT 4 + #define Y_DISABLE_BIT 10 + #define Z_DISABLE_BIT 19 + #define A_DISABLE_BIT 21 + //#define B_DISABLE_BIT 29 + //#define C_DISABLE_BIT NotUsed + #define STEPPERS_DISABLE_MASK ((1<FIODIR + #define LIMIT_PIN LPC_GPIO1->FIOPIN + #define LIMIT_PORT LPC_GPIO1->FIOPIN + #define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=25 + #define Y_LIMIT_BIT 26 // Y-MIN=26, Y-MAX=27 + #define Z_LIMIT_BIT 29 // Z-MIN=28, Z-MAX=29 + #define A_LIMIT_BIT 28 // reuse p1.28, as z-min is not often used + //#define B_LIMIT_BIT NotUsed + //#define C_LIMIT_BIT NotUsed + #define LIMIT_MASK ((1<FIODIR + #define STEP_PORT LPC_GPIO2->FIOPIN + #define X_STEP_BIT 1 + #define Y_STEP_BIT 2 + #define Z_STEP_BIT 3 + #define A_STEP_BIT 0 + #define STEP_MASK ((1<FIODIR + #define DIRECTION_PORT LPC_GPIO0->FIOPIN + #define X_DIRECTION_BIT 11 + #define Y_DIRECTION_BIT 20 + #define Z_DIRECTION_BIT 22 + #define A_DIRECTION_BIT 5 + #define DIRECTION_MASK ((1<FIODIR + #define STEPPERS_DISABLE_PORT LPC_GPIO0->FIOPIN + #define X_DISABLE_BIT 10 + #define Y_DISABLE_BIT 19 + #define Z_DISABLE_BIT 21 + #define A_DISABLE_BIT 4 + #define STEPPERS_DISABLE_MASK ((1<FIODIR + #define LIMIT_PIN LPC_GPIO1->FIOPIN + #define LIMIT_PORT LPC_GPIO1->FIOPIN + #define X_LIMIT_BIT 24 // X-MIN=24, X-MAX=27 + #define Y_LIMIT_BIT 25 // Y-MIN=25, Y-MAX=28 + #define Z_LIMIT_BIT 26 // Z-MIN=26, Z-MAX=29 + #define A_LIMIT_BIT 27 // reuse p1.27, as X-MAX is not used + #define LIMIT_MASK ((1<