136 lines
4.0 KiB
C
136 lines
4.0 KiB
C
/*
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interrupt.c - replacement for the avr library of the same name to provide
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dummy register variables
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Part of Grbl Simulator
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Copyright (c) 2012 Jens Geisler
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Grbl is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Grbl is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Grbl. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "interrupt.h"
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#include "io.h"
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//pseudo-Interrupt vector table
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isr_fp compa_vect[6]={0};
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isr_fp compb_vect[6]={0};
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isr_fp ovf_vect[6]={0};
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void sei() {io.sreg|=SEI;}
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void cli() {io.sreg&=~SEI;}
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int16_t sim_scaling[8]={0,1,8,64,256,1024,1,1}; //clock scalars
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//Timer/Counter modes: these are incomplete, but enough for this application
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enum sim_wgm_mode {
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wgm_NORMAL,
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wgm_CTC,
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wgm_FAST_PWM,
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wgm_PHASE_PWM,
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wgm_PH_F_PWM,
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wgm_RESERVED
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};
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enum sim_wgm_mode sim_wgm0[4] = {wgm_NORMAL,wgm_PHASE_PWM,wgm_CTC,wgm_FAST_PWM};
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enum sim_wgm_mode sim_wgmN[8] = {wgm_NORMAL,wgm_PHASE_PWM,wgm_PHASE_PWM,wgm_PH_F_PWM,
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wgm_CTC, wgm_FAST_PWM, wgm_FAST_PWM, wgm_FAST_PWM};
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void timer_interrupts() {
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int i;
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uint8_t ien = io.sreg&SEI; //interrupts enabled?
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io.prescaler++;
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//all clocks
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for (i=0;i<2;i++){
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uint8_t cs = io.tccrb[i]&7; //clock select bits
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int16_t increment = sim_scaling[cs];
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//check scaling to see if timer fires
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if (increment && (io.prescaler&(increment-1))==0) {
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//select waveform generation mode
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enum sim_wgm_mode mode;
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if (i==0 || i==2) { //(T0 and T2 are different from rest)
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uint8_t wgm = io.tccra[i]&3; //look at low 2 bits
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mode = sim_wgm0[wgm];
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}
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else {
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uint8_t wgm = ((io.tccrb[i]&8)>>1) | (io.tccra[i]&3); //only using 3 bits for now
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mode = sim_wgmN[wgm];
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}
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//tick
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io.tcnt[i]++;
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//comparators
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if ((io.timsk[i]&(1<<SIM_OCA)) && io.tcnt[i]==io.ocra[i]) io.tifr[i]|=(1<<SIM_OCA);
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if ((io.timsk[i]&(1<<SIM_OCB)) && io.tcnt[i]==io.ocrb[i]) io.tifr[i]|=(1<<SIM_OCB);
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if ((io.timsk[i]&(1<<SIM_OCC)) && io.tcnt[i]==io.ocrc[i]) io.tifr[i]|=(1<<SIM_OCC);
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switch (mode) {
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case wgm_NORMAL: //Normal mode
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if (i==0) io.tcnt[i]&=0xFF; //timer0 is 8 bit;
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if (i==2) io.tcnt[i]&=0xFF; //timer2 is 8 bit;
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if (io.tcnt[i]==0) io.tifr[i]|=(1<<SIM_TOV);
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break;
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case wgm_CTC: //CTC mode
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if (io.tcnt[i]==io.ocra[i]) io.tcnt[i]=0;
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break;
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default: //unsupported
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break;
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}
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//call any triggered interupts
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if (ien && io.tifr[i]) {
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if (compa_vect[i] && (io.tifr[i]&(1<<SIM_OCA))) {
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compa_vect[i]();
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io.tifr[i]&=~(1<<SIM_OCA);
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//TODO: insert port_monitor call here
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}
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if (compb_vect[i] && (io.tifr[i]&(1<<SIM_OCB))) {
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compb_vect[i]();
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io.tifr[i]&=~(1<<SIM_OCB);
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}
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if (ovf_vect[i] && (io.tifr[i]&(1<<SIM_TOV))) {
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ovf_vect[i]();
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io.tifr[i]&=~(1<<SIM_TOV);
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}
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}
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}
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}
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//// TODO for more complete timer sim.
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// pwm modes. (only used for variable spindle, I think).
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// -- would require fixing wgm mode for Timers1..5
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// -- phase correct modes need updown counter.
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// output pins (also only for variable spindle, I think).
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//// Other chip features not needed yet for grbl:
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// writes to TCNT0 prevent compare match (need write detector.)
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// force output compare (unused)
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// input capture (unused and how would we signal it?)
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// define the other output compare registers.
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// usercode can clear unhandled interrupt flags by writing 1.
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// --(this may be impossible, since bit was 1 before the write.)
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// prescaler reset.
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// maybe need to cli on interrupt entry
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}
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