540 lines
22 KiB
C
540 lines
22 KiB
C
/**************************************************************************//**
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* @file system_LPC17xx.c
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
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* for the NXP LPC17xx Device Series
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* @version V1.03
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* @date 07. October 2009
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*
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* @note
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include <stdint.h>
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#include "LPC17xx.h"
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- Clock Configuration ----------------------------------
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//
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// <e> Clock Configuration
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// <h> System Controls and Status Register (SCS)
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// <o1.4> OSCRANGE: Main Oscillator Range Select
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// <0=> 1 MHz to 20 MHz
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// <1=> 15 MHz to 24 MHz
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// <e1.5> OSCEN: Main Oscillator Enable
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// </e>
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// </h>
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//
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// <h> Clock Source Select Register (CLKSRCSEL)
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// <o2.0..1> CLKSRC: PLL Clock Source Selection
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// <0=> Internal RC oscillator
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// <1=> Main oscillator
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// <2=> RTC oscillator
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// </h>
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//
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// <e3> PLL0 Configuration (Main PLL)
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// <h> PLL0 Configuration Register (PLL0CFG)
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// <i> F_cco0 = (2 * M * F_in) / N
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// <i> F_in must be in the range of 32 kHz to 50 MHz
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// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
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// <o4.0..14> MSEL: PLL Multiplier Selection
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// <6-32768><#-1>
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// <i> M Value
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// <o4.16..23> NSEL: PLL Divider Selection
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// <1-256><#-1>
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// <i> N Value
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// </h>
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// </e>
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//
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// <e5> PLL1 Configuration (USB PLL)
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// <h> PLL1 Configuration Register (PLL1CFG)
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// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
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// <i> F_cco1 = F_osc * M * 2 * P
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// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
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// <o6.0..4> MSEL: PLL Multiplier Selection
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// <1-32><#-1>
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// <i> M Value (for USB maximum value is 4)
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// <o6.5..6> PSEL: PLL Divider Selection
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// <0=> 1
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// <1=> 2
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// <2=> 4
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// <3=> 8
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// <i> P Value
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// </h>
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// </e>
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//
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// <h> CPU Clock Configuration Register (CCLKCFG)
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// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
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// <3-256><#-1>
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// </h>
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//
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// <h> USB Clock Configuration Register (USBCLKCFG)
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// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
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// <0-15>
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// <i> Divide is USBSEL + 1
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// </h>
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//
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// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
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// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 6
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// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 6
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// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 6
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// </h>
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//
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// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
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// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// </h>
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//
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// <h> Power Control for Peripherals Register (PCONP)
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// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
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// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
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// <o11.3> PCUART0: UART 0 power/clock enable
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// <o11.4> PCUART1: UART 1 power/clock enable
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// <o11.6> PCPWM1: PWM 1 power/clock enable
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// <o11.7> PCI2C0: I2C interface 0 power/clock enable
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// <o11.8> PCSPI: SPI interface power/clock enable
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// <o11.9> PCRTC: RTC power/clock enable
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// <o11.10> PCSSP1: SSP interface 1 power/clock enable
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// <o11.12> PCAD: A/D converter power/clock enable
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// <o11.13> PCCAN1: CAN controller 1 power/clock enable
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// <o11.14> PCCAN2: CAN controller 2 power/clock enable
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// <o11.15> PCGPIO: GPIOs power/clock enable
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// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
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// <o11.17> PCMC: Motor control PWM power/clock enable
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// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
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// <o11.19> PCI2C1: I2C interface 1 power/clock enable
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// <o11.21> PCSSP0: SSP interface 0 power/clock enable
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// <o11.22> PCTIM2: Timer 2 power/clock enable
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// <o11.23> PCTIM3: Timer 3 power/clock enable
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// <o11.24> PCUART2: UART 2 power/clock enable
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// <o11.25> PCUART3: UART 3 power/clock enable
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// <o11.26> PCI2C2: I2C interface 2 power/clock enable
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// <o11.27> PCI2S: I2S interface power/clock enable
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// <o11.29> PCGPDMA: GP DMA function power/clock enable
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// <o11.30> PCENET: Ethernet block power/clock enable
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// <o11.31> PCUSB: USB interface power/clock enable
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// </h>
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//
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// <h> Clock Output Configuration Register (CLKOUTCFG)
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// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
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// <0=> CPU clock
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// <1=> Main oscillator
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// <2=> Internal RC oscillator
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// <3=> USB clock
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// <4=> RTC oscillator
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// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
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// <1-16><#-1>
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// <o12.8> CLKOUT_EN: CLKOUT enable control
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// </h>
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//
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// </e>
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*/
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#define CLOCK_SETUP 1
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#define SCS_Val 0x00000020
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#define CLKSRCSEL_Val 0x00000001
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#define PLL0_SETUP 1
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#define PLL0CFG_Val 0x00050063
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#define PLL1_SETUP 1
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#define PLL1CFG_Val 0x00000023
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#define CCLKCFG_Val 0x00000003
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#define USBCLKCFG_Val 0x00000000
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#define PCLKSEL0_Val 0x00000014
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#define PCLKSEL1_Val 0x00005000
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#define PCONP_Val 0x04E887DE
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#define CLKOUTCFG_Val 0x00000000
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/*--------------------- Flash Accelerator Configuration ----------------------
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//
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// <e> Flash Accelerator Configuration
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// <o1.0..1> FETCHCFG: Fetch Configuration
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// <0=> Instruction fetches from flash are not buffered
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// <1=> One buffer is used for all instruction fetch buffering
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// <2=> All buffers may be used for instruction fetch buffering
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// <3=> Reserved (do not use this setting)
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// <o1.2..3> DATACFG: Data Configuration
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// <0=> Data accesses from flash are not buffered
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// <1=> One buffer is used for all data access buffering
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// <2=> All buffers may be used for data access buffering
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// <3=> Reserved (do not use this setting)
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// <o1.4> ACCEL: Acceleration Enable
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// <o1.5> PREFEN: Prefetch Enable
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// <o1.6> PREFOVR: Prefetch Override
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// <o1.12..15> FLASHTIM: Flash Access Time
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// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
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// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
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// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
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// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
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// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
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// <5=> 6 CPU clocks (for any CPU clock)
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// </e>
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*/
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#define FLASH_SETUP 1
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#define FLASHCFG_Val 0x0000503A
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/*
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//-------- <<< end of configuration section >>> ------------------------------
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*/
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/*----------------------------------------------------------------------------
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Check the register settings
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*----------------------------------------------------------------------------*/
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#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
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#define CHECK_RSVD(val, mask) (val & mask)
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/* Clock Configuration -------------------------------------------------------*/
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#if (CHECK_RSVD((SCS_Val), ~0x00000030))
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#error "SCS: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
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#error "CLKSRCSEL: Value out of range!"
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#endif
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#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
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#error "PLL0CFG: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
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#error "PLL1CFG: Invalid values of reserved bits!"
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#endif
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#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
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#error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
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#endif
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#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
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#error "USBCLKCFG: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
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#error "PCLKSEL0: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
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#error "PCLKSEL1: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((PCONP_Val), 0x10100821))
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#error "PCONP: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
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#error "CLKOUTCFG: Invalid values of reserved bits!"
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#endif
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/* Flash Accelerator Configuration -------------------------------------------*/
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#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
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#error "FLASHCFG: Invalid values of reserved bits!"
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#endif
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/*----------------------------------------------------------------------------
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DEFINES
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*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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#define XTAL (12000000UL) /* Oscillator frequency */
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#define OSC_CLK ( XTAL) /* Main oscillator frequency */
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#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
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#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
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/* F_cco0 = (2 * M * F_in) / N */
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#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
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#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
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#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
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#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
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/* Determine core clock frequency according to settings */
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#if (PLL0_SETUP)
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#if ((CLKSRCSEL_Val & 0x03) == 1)
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#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
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#elif ((CLKSRCSEL_Val & 0x03) == 2)
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#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
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#else
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#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
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#endif
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#else
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#if ((CLKSRCSEL_Val & 0x03) == 1)
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#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
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#elif ((CLKSRCSEL_Val & 0x03) == 2)
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#define __CORE_CLK (RTC_CLK / __CCLK_DIV)
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#else
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#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
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#endif
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#endif
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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*----------------------------------------------------------------------------*/
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uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
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/*----------------------------------------------------------------------------
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Clock functions
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*----------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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{
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/* Determine clock frequency according to clock register values */
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if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
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switch (LPC_SC->CLKSRCSEL & 0x03) {
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case 0: /* Int. RC oscillator => PLL0 */
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case 3: /* Reserved, default to Int. RC */
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SystemCoreClock = (IRC_OSC *
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((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
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(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
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((LPC_SC->CCLKCFG & 0xFF)+ 1));
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break;
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case 1: /* Main oscillator => PLL0 */
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SystemCoreClock = (OSC_CLK *
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((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
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(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
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((LPC_SC->CCLKCFG & 0xFF)+ 1));
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break;
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case 2: /* RTC oscillator => PLL0 */
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SystemCoreClock = (RTC_CLK *
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((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
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(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
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((LPC_SC->CCLKCFG & 0xFF)+ 1));
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break;
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}
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} else {
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switch (LPC_SC->CLKSRCSEL & 0x03) {
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case 0: /* Int. RC oscillator => PLL0 */
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case 3: /* Reserved, default to Int. RC */
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SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
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break;
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case 1: /* Main oscillator => PLL0 */
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SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
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break;
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case 2: /* RTC oscillator => PLL0 */
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SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
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break;
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}
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}
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|
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit (void)
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{
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#if (CLOCK_SETUP) /* Clock Setup */
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LPC_SC->SCS = SCS_Val;
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if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
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while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
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}
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|
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LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
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|
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#if (PLL0_SETUP)
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LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
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|
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LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
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LPC_SC->PLL0FEED = 0xAA;
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LPC_SC->PLL0FEED = 0x55;
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|
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LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
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LPC_SC->PLL0FEED = 0xAA;
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LPC_SC->PLL0FEED = 0x55;
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|
while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
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|
|
|
LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
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|
LPC_SC->PLL0FEED = 0xAA;
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|
LPC_SC->PLL0FEED = 0x55;
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while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
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|
#endif
|
|
|
|
#if (PLL1_SETUP)
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|
LPC_SC->PLL1CFG = PLL1CFG_Val;
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|
LPC_SC->PLL1FEED = 0xAA;
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|
LPC_SC->PLL1FEED = 0x55;
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|
|
|
LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
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|
LPC_SC->PLL1FEED = 0xAA;
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|
LPC_SC->PLL1FEED = 0x55;
|
|
while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
|
|
|
|
LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
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|
LPC_SC->PLL1FEED = 0xAA;
|
|
LPC_SC->PLL1FEED = 0x55;
|
|
while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
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|
#else
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|
LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
|
|
#endif
|
|
|
|
LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
|
|
LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
|
|
|
|
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
|
|
|
|
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
|
|
#endif
|
|
|
|
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
|
|
LPC_SC->FLASHCFG = FLASHCFG_Val;
|
|
#endif
|
|
}
|