ashelly
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9b37637ae6
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Bug fixes for timers, added some wdt support for limit debounce.
- Typo in timer def,
- Handle 8 bit timers correctly,
- Don't skip TOP count in CTC mode
- added SREG for atomic bit operations
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2014-07-10 13:01:03 -04:00 |
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Sonny Jeon
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23ed7b6d4b
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Merge branch 'dev' into edge
Conflicts:
sim/simulator.c
sim/simulator.h
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2014-07-09 09:52:57 -06:00 |
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ashelly
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8c9f3bca65
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Total rework of simulator for dev branch. Create separate thread for interrupt processes. Tick-accurate simulation of timers. Non-blocking character input for running in realtime mode. Decouple hardware sim from grbl code as much as possible. Expanded command line options. Provisions for cross-platform solution.
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2014-07-04 11:14:54 -04:00 |
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michmerr
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59e906f7e8
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Simplify setting of STATE_CYCLE and ISR interval.
Set sys.state to STATE_CYCLE directly instead of calling back to
st_wakeup().
Convert get_step_time() to a constant and rename it to ISR_INTERVAL.
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2014-01-28 11:37:31 -08:00 |
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michmerr
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783100db7d
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Make sure that cycle_start state is set before simulating steps.
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2014-01-22 22:30:08 -08:00 |
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Jens Geisler
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ea09ddba99
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changed atomic access for updating the acceleration profile
the stepper interrupt is only halted when necessary and for the shortest
time possible (8% cycle time)
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2013-02-22 16:36:27 +01:00 |
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Jens Geisler
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87864cce19
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added counter for planner steps
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2013-02-20 15:04:26 +01:00 |
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Jens Geisler
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5e76136dd3
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relaunch ontop of latest grbl edge
code very messy but tested
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2013-01-17 13:06:51 +01:00 |
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