Merge tag 'v1.1f.20170131'
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@ -44,11 +44,17 @@
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// NOTE: AMASS cutoff frequency multiplied by ISR overdrive factor must not exceed maximum step frequency.
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// NOTE: Current settings are set to overdrive the ISR to no more than 16kHz, balancing CPU overhead
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// and timer accuracy. Do not alter these settings unless you know what you are doing.
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#define MAX_AMASS_LEVEL 3
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// AMASS_LEVEL0: Normal operation. No AMASS. No upper cutoff frequency. Starts at LEVEL1 cutoff frequency.
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#define AMASS_LEVEL1 (F_CPU/8000) // Over-drives ISR (x2). Defined as F_CPU/(Cutoff frequency in Hz)
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#define AMASS_LEVEL2 (F_CPU/4000) // Over-drives ISR (x4)
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#define AMASS_LEVEL3 (F_CPU/2000) // Over-drives ISR (x8)
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#ifdef ADAPTIVE_MULTI_AXIS_STEP_SMOOTHING
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#define MAX_AMASS_LEVEL 3
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// AMASS_LEVEL0: Normal operation. No AMASS. No upper cutoff frequency. Starts at LEVEL1 cutoff frequency.
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#define AMASS_LEVEL1 (F_CPU/8000) // Over-drives ISR (x2). Defined as F_CPU/(Cutoff frequency in Hz)
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#define AMASS_LEVEL2 (F_CPU/4000) // Over-drives ISR (x4)
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#define AMASS_LEVEL3 (F_CPU/2000) // Over-drives ISR (x8)
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#if MAX_AMASS_LEVEL <= 0
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error "AMASS must have 1 or more levels to operate correctly."
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#endif
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#endif
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// Stores the planner block Bresenham algorithm execution data for the segments in the segment
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@ -646,8 +652,8 @@ void st_prep_buffer()
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st_prep_block->direction_bits = pl_block->direction_bits;
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uint8_t idx;
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#ifndef ADAPTIVE_MULTI_AXIS_STEP_SMOOTHING
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for (idx=0; idx<N_AXIS; idx++) { st_prep_block->steps[idx] = pl_block->steps[idx]; }
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st_prep_block->step_event_count = pl_block->step_event_count;
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for (idx=0; idx<N_AXIS; idx++) { st_prep_block->steps[idx] = (pl_block->steps[idx] << 1); }
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st_prep_block->step_event_count = (pl_block->step_event_count << 1);
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#else
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// With AMASS enabled, simply bit-shift multiply all Bresenham data by the max AMASS
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// level, such that we never divide beyond the original data anywhere in the algorithm.
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