Port stepper

This commit is contained in:
Todd Fleming
2017-01-08 16:12:24 -05:00
parent fdf6e31218
commit d4cbac2a5c
4 changed files with 70 additions and 60 deletions

View File

@ -28,28 +28,14 @@ extern DummyReg EECR;
extern DummyReg EEDR;
extern DummyReg EEMPE;
extern DummyReg EEPE;
extern DummyReg OCIE0A;
extern DummyReg OCIE0B;
extern DummyReg OCIE1A;
extern DummyReg OCR1A;
extern DummyReg OCR2A;
extern DummyReg PCICR;
extern DummyReg PCIE0;
extern DummyReg PCIE1;
extern DummyReg PCMSK0;
extern DummyReg PCMSK1;
extern DummyReg SREG;
extern DummyReg TCCR0A;
extern DummyReg TCCR0B;
extern DummyReg TCCR1A;
extern DummyReg TCCR1B;
extern DummyReg TCCRA;
extern DummyReg TCCR2A;
extern DummyReg TCCR2B;
extern DummyReg TCNT0;
extern DummyReg TIMSK0;
extern DummyReg TIMSK1;
extern DummyReg TOIE0;
extern DummyReg UCSR0A;
extern DummyReg UCSR0B;
@ -68,11 +54,7 @@ static const int COM2A1 = 0;
static const int COM2B0 = 0;
static const int COM2B1 = 0;
static const int CS01 = 0;
static const int CS10 = 0;
static const int CS11 = 0;
static const int CS12 = 0;
static const int CS22 = 0;
static const int CS22 = 0;
static const int EEMWE = 0;
static const int EERE = 0;
static const int EEWE = 0;

View File

@ -24,15 +24,25 @@
void delay_init();
// Get current time in clock cycles
inline uint32_t get_time()
{
return LPC_TIM3->TC;
}
// Wait until get_time() is numCycles past startTime. Handles timer wrap.
inline void delay_loop(uint32_t startTime, uint32_t numCycles)
{
while (get_time() - startTime < numCycles)
;
}
inline void delay_us(uint32_t us)
{
uint32_t start = LPC_TIM3->TC;
uint32_t cycles = uint32_t(uint64_t(SystemCoreClock) * us / 1000000);
while (LPC_TIM3->TC - start < cycles)
;
delay_loop(get_time(), uint32_t(uint64_t(SystemCoreClock) * us / 1'000'000));
}
inline void delay_ms(uint32_t ms)
{
return delay_us(ms * 1000);
delay_loop(get_time(), uint32_t(uint64_t(SystemCoreClock) * ms / 1000));
}