Total rework of simulator for dev branch. Create separate thread for interrupt processes. Tick-accurate simulation of timers. Non-blocking character input for running in realtime mode. Decouple hardware sim from grbl code as much as possible. Expanded command line options. Provisions for cross-platform solution.
This commit is contained in:
ashelly
@ -21,23 +21,115 @@
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*/
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#include "interrupt.h"
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#include "io.h"
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//pseudo-Interrupt vector table
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isr_fp compa_vect[6]={0};
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isr_fp compb_vect[6]={0};
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isr_fp ovf_vect[6]={0};
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void sei() {io.sreg|=SEI;}
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void cli() {io.sreg&=~SEI;}
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int16_t sim_scaling[8]={0,1,8,64,256,1024,1,1}; //clock scalars
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//Timer/Counter modes: these are incomplete, but enough for this application
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enum sim_wgm_mode {
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wgm_NORMAL,
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wgm_CTC,
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wgm_FAST_PWM,
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wgm_PHASE_PWM,
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wgm_PH_F_PWM,
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wgm_RESERVED
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};
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enum sim_wgm_mode sim_wgm0[4] = {wgm_NORMAL,wgm_PHASE_PWM,wgm_CTC,wgm_FAST_PWM};
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enum sim_wgm_mode sim_wgmN[8] = {wgm_NORMAL,wgm_PHASE_PWM,wgm_PHASE_PWM,wgm_PH_F_PWM,
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wgm_CTC, wgm_FAST_PWM, wgm_FAST_PWM, wgm_FAST_PWM};
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void timer_interrupts() {
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int i;
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uint8_t ien = io.sreg&SEI; //interrupts enabled?
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io.prescaler++;
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//all clocks
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for (i=0;i<2;i++){
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uint8_t cs = io.tccrb[i]&7; //clock select bits
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int16_t increment = sim_scaling[cs];
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//check scaling to see if timer fires
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if (increment && (io.prescaler&(increment-1))==0) {
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//select waveform generation mode
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enum sim_wgm_mode mode;
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if (i==0 || i==2) { //(T0 and T2 are different from rest)
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uint8_t wgm = io.tccra[i]&3; //look at low 2 bits
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mode = sim_wgm0[wgm];
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}
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else {
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uint8_t wgm = ((io.tccrb[i]&8)>>1) | (io.tccra[i]&3); //only using 3 bits for now
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mode = sim_wgmN[wgm];
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}
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//tick
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io.tcnt[i]++;
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//comparators
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if ((io.timsk[i]&(1<<SIM_OCA)) && io.tcnt[i]==io.ocra[i]) io.tifr[i]|=(1<<SIM_OCA);
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if ((io.timsk[i]&(1<<SIM_OCB)) && io.tcnt[i]==io.ocrb[i]) io.tifr[i]|=(1<<SIM_OCB);
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if ((io.timsk[i]&(1<<SIM_OCC)) && io.tcnt[i]==io.ocrc[i]) io.tifr[i]|=(1<<SIM_OCC);
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switch (mode) {
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case wgm_NORMAL: //Normal mode
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if (i==0) io.tcnt[i]&=0xFF; //timer0 is 8 bit;
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if (i==2) io.tcnt[i]&=0xFF; //timer2 is 8 bit;
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if (io.tcnt[i]==0) io.tifr[i]|=(1<<SIM_TOV);
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break;
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case wgm_CTC: //CTC mode
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if (io.tcnt[i]==io.ocra[i]) io.tcnt[i]=0;
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break;
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default: //unsupported
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break;
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}
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//call any triggered interupts
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if (ien && io.tifr[i]) {
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if (compa_vect[i] && (io.tifr[i]&(1<<SIM_OCA))) {
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compa_vect[i]();
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io.tifr[i]&=~(1<<SIM_OCA);
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//TODO: insert port_monitor call here
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}
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if (compb_vect[i] && (io.tifr[i]&(1<<SIM_OCB))) {
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compb_vect[i]();
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io.tifr[i]&=~(1<<SIM_OCB);
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}
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if (ovf_vect[i] && (io.tifr[i]&(1<<SIM_TOV))) {
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ovf_vect[i]();
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io.tifr[i]&=~(1<<SIM_TOV);
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}
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}
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}
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}
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//// TODO for more complete timer sim.
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// pwm modes. (only used for variable spindle, I think).
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// -- would require fixing wgm mode for Timers1..5
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// -- phase correct modes need updown counter.
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// output pins (also only for variable spindle, I think).
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//// Other chip features not needed yet for grbl:
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// writes to TCNT0 prevent compare match (need write detector.)
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// force output compare (unused)
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// input capture (unused and how would we signal it?)
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// define the other output compare registers.
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// usercode can clear unhandled interrupt flags by writing 1.
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// --(this may be impossible, since bit was 1 before the write.)
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// prescaler reset.
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// maybe need to cli on interrupt entry
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}
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// dummy register variables
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uint16_t timsk0;
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uint16_t timsk1;
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uint16_t timsk2;
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uint16_t ocr1a;
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uint16_t ocr2a;
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uint16_t tcnt0;
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uint16_t tcnt2;
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uint16_t tccr0b;
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uint16_t tccr2b;
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uint16_t tccr1b;
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uint16_t tccr0a;
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uint16_t tccr1a;
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uint16_t tccr2a;
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uint16_t pcmsk0;
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uint16_t pcicr;
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void sei() {};
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void cli() {};
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@ -24,60 +24,33 @@
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#ifndef interrupt_h
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#define interrupt_h
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#include <inttypes.h>
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// dummy register variables
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extern uint16_t timsk0;
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extern uint16_t timsk1;
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extern uint16_t timsk2;
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extern uint16_t tcnt0;
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extern uint16_t tcnt2;
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extern uint16_t tccr0b;
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extern uint16_t tccr0a;
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extern uint16_t tccr2a;
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extern uint16_t tccr2b;
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extern uint16_t tccr1b;
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extern uint16_t tccr1a;
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extern uint16_t ocr1a;
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extern uint16_t ocr2a;
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extern uint16_t pcmsk0;
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extern uint16_t pcicr;
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// macros to turn avr interrupts into regular functions
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#define TIMER1_COMPA_vect
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//#define TIMER1_COMPA_vect
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#define ISR(a) void interrupt_ ## a ()
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// enable interrupts does nothing in the simulation environment
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// Stub of the timer interrupt functions we need
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void interrupt_TIMER0_COMPA_vect();
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void interrupt_TIMER1_COMPA_vect();
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void interrupt_TIMER0_OVF_vect();
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void interrupt_SERIAL_UDRE();
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void interrupt_SERIAL_RX();
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//pseudo-Interrupt vector table
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typedef void(*isr_fp)(void);
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extern isr_fp compa_vect[6];
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extern isr_fp compb_vect[6];
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extern isr_fp ovf_vect[6];
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// enable interrupts now does something in the simulation environment
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#define SEI 0x80
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void sei();
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void cli();
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// dummy macros for interrupt related registers
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#define TIMSK0 timsk0
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#define TIMSK1 timsk1
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#define TIMSK2 timsk2
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#define OCR1A ocr1a
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#define OCR2A ocr2a
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#define OCIE1A 0
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#define OCIE2A 0
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#define TCNT0 tcnt0
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#define TCNT2 tcnt2
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#define TCCR0B tccr0b
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#define TCCR0A tccr0a
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#define TCCR1A tccr1a
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#define TCCR1B tccr1b
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#define TCCR2A tccr2a
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#define TCCR2B tccr2b
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#define CS21 0
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#define CS10 0
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#define WGM13 0
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#define WGM12 0
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#define WGM11 0
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#define WGM10 0
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#define WGM21 0
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#define COM1A0 0
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#define COM1B0 0
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#define TOIE0 0
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#define TOIE2 0
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#define PCICR pcicr
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//simulate timer operation
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void timer_interrupts();
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#endif
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4
sim/avr/io.c
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4
sim/avr/io.c
Normal file
@ -0,0 +1,4 @@
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#include "io.h"
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// dummy register variables
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volatile io_sim_t io={{0}};
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182
sim/avr/io.h
182
sim/avr/io.h
@ -1,5 +1,6 @@
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/*
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io.h - dummy replacement for the avr include of the same name
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interrupt.h - replacement for the avr include of the same name to provide
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dummy register variables and macros
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Part of Grbl Simulator
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@ -19,3 +20,182 @@
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along with Grbl. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef io_h
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#define io_h
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#include <inttypes.h>
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union hilo16 {
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uint16_t w;
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struct {
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uint8_t l; //TODO: check that these are right order on x86. Doesn't matter for current usage, but might someday
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uint8_t h;
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};
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};
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enum {
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SIM_A, SIM_B, SIM_C, SIM_D, SIM_E,
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SIM_F, SIM_G, SIM_H, SIM_J, SIM_K, SIM_L,
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SIM_PORT_COUNT
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};
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#define SIM_N_TIMERS 6
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// dummy register variables
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typedef struct io_sim {
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uint8_t ddr[SIM_PORT_COUNT];
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uint8_t port[SIM_PORT_COUNT];
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uint8_t pin[SIM_PORT_COUNT];
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uint8_t timsk[SIM_N_TIMERS];
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uint16_t ocra[SIM_N_TIMERS];
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uint16_t ocrb[SIM_N_TIMERS];
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uint16_t ocrc[SIM_N_TIMERS];
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uint16_t tcnt[SIM_N_TIMERS]; //tcint0 is really only 8bit
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uint8_t tccra[SIM_N_TIMERS];
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uint8_t tccrb[SIM_N_TIMERS];
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uint8_t tifr[SIM_N_TIMERS];
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uint8_t pcicr;
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uint8_t pcmsk[3];
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uint8_t ucsr0[3];
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uint8_t udr[3];
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union hilo16 ubrr0;
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uint16_t prescaler; //continuously running
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uint8_t sreg;
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} io_sim_t;
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volatile extern io_sim_t io;
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// dummy macros for interrupt related registers
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#define PORTA io.port[SIM_A]
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#define PORTB io.port[SIM_B]
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#define PORTC io.port[SIM_C]
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#define PORTD io.port[SIM_D]
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#define PORTE io.port[SIM_E]
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#define PORTF io.port[SIM_F]
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#define PORTG io.port[SIM_G]
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#define PORTH io.port[SIM_H]
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#define PORTJ io.port[SIM_J]
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#define PORTK io.port[SIM_K]
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#define PORTL io.port[SIM_L]
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#define DDRA io.ddr[SIM_A]
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#define DDRB io.ddr[SIM_B]
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#define DDRC io.ddr[SIM_C]
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#define DDRD io.ddr[SIM_D]
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#define DDRE io.ddr[SIM_E]
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#define DDRF io.ddr[SIM_F]
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#define DDRG io.ddr[SIM_G]
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#define DDRH io.ddr[SIM_H]
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#define DDRJ io.ddr[SIM_J]
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#define PINA io.pin[SIM_A]
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#define PINB io.pin[SIM_B]
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#define PINC io.pin[SIM_C]
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#define PIND io.pin[SIM_D]
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#define PINE io.pin[SIM_E]
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#define PINF io.pin[SIM_F]
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#define PING io.pin[SIM_G]
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#define PINH io.pin[SIM_H]
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#define PINJ io.pin[SIM_J]
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#define PINK io.pin[SIM_K]
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#define PINL io.pin[SIM_L]
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#define TIMSK0 io.timsk[0]
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#define TIMSK1 io.timsk[1]
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#define TIMSK2 io.timsk[2]
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#define TIMSK3 io.timsk[3]
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#define TIMSK4 io.timsk[4]
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#define TIMSK5 io.timsk[5]
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#define SIM_TOV 0
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#define SIM_OCA 1
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#define SIM_OCB 2
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#define SIM_OCC 3
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#define SIM_ICI 5
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#define OCIE0A SIM_OCA
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#define OCIE0B SIM_OCB
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#define TOIE0 SIM_TOV
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#define ICIE1 SIM_ICI
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#define OCIE1C SIM_OCC
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#define OCIE1B SIM_OCB
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#define OCIE1A SIM_OCA
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#define TOIE1 SIM_ICI
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#define ICIE2 SIM_ICI
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#define OCIE2C SIM_OCC
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#define OCIE2B SIM_OCB
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#define OCIE2A SIM_OCA
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#define TOIE2 SIM_TOV
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#define OCR0A io.ocra[0]
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#define OCR1A io.ocra[1]
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#define OCR2A io.ocra[2]
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//There are more..
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#define TCNT0 io.tcnt[0]
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#define TCNT1 io.tcnt[1]
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#define TCNT2 io.tcnt[2]
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#define TCCR0B io.tccra[0]
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#define TCCR0A io.tccrb[0]
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#define TCCR1A io.tccra[1]
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#define TCCR1B io.tccrb[1]
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#define TCCR2A io.tccra[2]
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#define TCCR2B io.tccrb[2]
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#define CS00 0
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#define CS01 1
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#define CS12 2
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#define CS11 1
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#define CS10 0
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#define CS21 1
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#define WGM13 4
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#define WGM12 3
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#define WGM11 1
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#define WGM10 0
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#define WGM21 1
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#define COM1A1 7
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#define COM1A0 6
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#define COM1B1 5
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#define COM1B0 4
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#define COM1C1 3
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#define COM1C0 2
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#define PCICR io.pcicr
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#define PCIE0 0
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#define PCIE1 1
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//serial channel
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#define UCSR0A io.ucsr0[SIM_A]
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#define UCSR0B io.ucsr0[SIM_B]
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#define UDR0 io.udr[0]
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#define UDRIE0 0
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#define RXCIE0 1
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#define RXEN0 2
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#define TXEN0 3
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#define U2X0 4
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#define UBRR0H io.ubrr0.h
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#define UBRR0L io.ubrr0.l
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#define PCMSK0 io.pcmsk[0]
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#define PCMSK1 io.pcmsk[1]
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#define PCMSK2 io.pcmsk[2]
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#endif
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1
sim/avr/wdt.h
Normal file
1
sim/avr/wdt.h
Normal file
@ -0,0 +1 @@
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uint16_t wdt;
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