ManuelW/grbl-LPC-CoreXY
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Fix #3: wrong port for limit switches

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This commit is contained in:
Todd Fleming 2017-04-08 14:57:31 -04:00
parent 612b781e3e
commit 5a862a5e30
2 changed files with 3 additions and 4 deletions
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1
README.md
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@ -20,7 +20,6 @@ Usage notes:
* Laser mode: ON ($32)
* Minimum S value: 0.0 ($31)
* Maximum S value: 1.0 ($30)
* Homing not tested
* Hard limits not yet ported
* Control inputs not yet ported (e.g. Cycle Start and Safety Door switches)

6
grbl/config.h
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@ -660,9 +660,9 @@
// Define homing/hard limit switch input pins and limit interrupt vectors.
// NOTE: All limit bit pins must be on the same port, but not on a port with other input pins (CONTROL).
#define LIMIT_DDR LPC_GPIO0->FIODIR
#define LIMIT_PIN LPC_GPIO0->FIOPIN
#define LIMIT_PORT LPC_GPIO0->FIOPIN
#define LIMIT_DDR LPC_GPIO1->FIODIR
#define LIMIT_PIN LPC_GPIO1->FIOPIN
#define LIMIT_PORT LPC_GPIO1->FIOPIN
#define X_LIMIT_BIT 25 // X-MIN=24, X-MAX=25
#define Y_LIMIT_BIT 27 // Y-MIN=26, Y-MAX=27
#define Z_LIMIT_BIT 29 // Z-MIN=28, Z-MAX=29