Planner execution time halved and bug fixes. Increased step rate limit to 30kHz.

- Planner execute speed has been more than halved from 4ms to 1.9ms
when computing a plan for a single line segment during arc generation.
This means that Grbl can now run through an arc (or complex curve)
twice as fast as before without starving the buffer. For 0.1mm arc
segments, this means about the theoretical feed rate limit is about
3000mm/min for arcs now.

- Increased the Ranade timer frequency to 30kHz, as there doesn't seem
to be any problems with increasing the frequency. This means that the
maximum step frequency is now back at 30kHz.

- Added Zen Toolworks 7x7 defaults.

stepper.c

@@ -106,8 +106,7 @@ void st_wake_up()
 // Stepper shutdown
 void st_go_idle() 
 {
-  // Disable stepper driver interrupt. Allow Timer2 to continue counting since COMPB may not be 
-  // finished. COMPB will disable itself when finished.
+  // Disable stepper driver interrupt. Allow Timer0 to finish. It will disable itself.
   TIMSK2 &= ~(1<<OCIE2A); // Disable Timer2 interrupt
   TCCR2B = 0; // Disable Timer2
 
@@ -131,7 +130,7 @@ void st_go_idle()
 // step event. However, the Ranade algorithm, as described, is susceptible to numerical round-off,
 // meaning that some axes steps may not execute for a given multi-axis motion.
 //   Grbl's algorithm slightly differs by using a single Ranade time-distance counter to manage
-// a Bresenham line algorithm for multi-axis step events and still ensure number of steps for
+// a Bresenham line algorithm for multi-axis step events which ensures the number of steps for
 // each axis are executed exactly. In other words, it uses a Bresenham within a Bresenham algorithm,
 // where one tracks time(Ranade) and the other steps.
 //   This interrupt pops blocks from the block_buffer and executes them by pulsing the stepper pins
@@ -146,7 +145,7 @@ ISR(TIMER2_COMPA_vect)
 // SPINDLE_ENABLE_PORT ^= 1<<SPINDLE_ENABLE_BIT; // Debug: Used to time ISR
   if (busy) { return; } // The busy-flag is used to avoid reentering this interrupt
   
-  // Set direction pins. Direction pins will always be set one timer tick before any step pulse.
+  // Set direction pins. New block dir will always be set one timer tick before any step pulse.
   STEPPING_PORT = (STEPPING_PORT & ~DIRECTION_MASK) | (out_bits & DIRECTION_MASK);
 
   // Pulse stepper pins, if flagged.
@@ -158,7 +157,7 @@ ISR(TIMER2_COMPA_vect)
   }
   
   busy = true;
-  sei();
+  sei(); // Re-enable interrupts. This ISR will still finish before returning to main program.
   
   // If there is no current block, attempt to pop one from the buffer
   if (current_block == NULL) {