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Add LPC17xx startup

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This commit is contained in:
Todd Fleming 2017-01-06 13:45:10 -05:00
parent 1cefc775b1
commit 179bfd6a9c
6 changed files with 2111 additions and 0 deletions
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1035
lpc17xx/LPC17xx.h Normal file
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5
lpc17xx/_exit.c Normal file
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void _exit()
{
while (1)
;
}

184
lpc17xx/lpc1769.ld Normal file
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/* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* THE AUTHORS SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. USE IT AT YOUR OWN RISK */
MEMORY
{
/* LPC1768 : 512k ROM + 64k SRAM */
/*------------------------------ */
/* On-chip ROM is a readable (r), executable region (x) */
/* On-chip SRAM is a readable (r), writable (w) and */
/* executable region (x) */
/* Main ROM region - 512k for LPC1768 */
IROM (rx) : ORIGIN = 0x00000000, LENGTH = 512k
/* local static RAM - 32k for LPC1756 */
IRAM0 (rwx) : ORIGIN = 0x10000000, LENGTH = 32k
/* AHB SRAM - 16k for LPC1756 - often used for USB */
IRAM1 (rwx) : ORIGIN = 0x2007C000, LENGTH = 16k
IRAM2 (rwx) : ORIGIN = 0x20080000, LENGTH = 16k
}
/* SECTION command : Define mapping of input sections */
/* into output sections. */
SECTIONS
{
/******************************************/
/* code section */
/* "normal" code */
.text :
{
KEEP(*(.isr_vector .isr_vector.*))
*(.text .text.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.gcc_except_table)
*(.rodata .rodata*)
*(.gnu.linkonce.r.*)
} >IROM
/******************************************/
/* .ctors .dtors are used for c++ constructors/destructors */
.ctors :
{
. = ALIGN(4);
PROVIDE(__ctors_start = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end = .);
} >IROM
.dtors :
{
. = ALIGN(4);
PROVIDE(__dtors_start = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end = .);
. = ALIGN(4);
/* End Of .text section */
_etext = .;
_sifastcode = .;
} >IROM
/**************************************************/
/* fastcode - copied at startup & executed in RAM */
.fastcode :
{
. = ALIGN (4);
_sfastcode = . ;
*(.glue_7t) *(.glue_7)
*(.fastcode)
/* add other modules here ... */
. = ALIGN (4);
_efastcode = . ;
_sidata = .;
} >IRAM0 AT>IROM
/******************************************/
/* This used for USB RAM section */
.usb_ram (NOLOAD):
{
*.o (USB_RAM)
} > IRAM1
/******************************************/
/* data section */
.data :
{
_sidata = LOADADDR (.data);
. = ALIGN(4);
_sdata = .;
*(vtable vtable.*)
*(.data .data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
_edata = . ;
} >IRAM0 AT>IROM
/******************************************/
/* For no-init variables section */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
__bss_start__ = .;
*(.bss .bss.*)
*(.gnu.linkonce.b*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
__bss_end__ = .;
} >IRAM0
/******************************************/
/* For stack section */
.stackarea (NOLOAD) :
{
. = ALIGN(8);
_sstack = .;
*(.stackarea .stackarea.*)
. = ALIGN(8);
_estack = .;
. = ALIGN(4);
_end = . ;
PROVIDE (end = .);
} > IRAM0
/******************************************/
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
/* .comment 0 : { *(.comment) } */
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

288
lpc17xx/startup_LPC17xx.c Normal file
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/****************************************************************************//**
* @file : startup_LPC17xx.c
* @brief : CMSIS Cortex-M3 Core Device Startup File
* @version : V1.01
* @date : 4. Feb. 2009
*
*----------------------------------------------------------------------------
*
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-Mx
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
// Mod by nio for the .fastcode part
#include "LPC17xx.h"
#define WEAK __attribute__ ((weak))
//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
/* System exception vector handler */
void WEAK Reset_Handler(void); /* Reset Handler */
void WEAK NMI_Handler(void); /* NMI Handler */
void WEAK HardFault_Handler(void); /* Hard Fault Handler */
void WEAK MemManage_Handler(void); /* MPU Fault Handler */
void WEAK BusFault_Handler(void); /* Bus Fault Handler */
void WEAK UsageFault_Handler(void); /* Usage Fault Handler */
void WEAK SVC_Handler(void); /* SVCall Handler */
void WEAK DebugMon_Handler(void); /* Debug Monitor Handler */
void WEAK PendSV_Handler(void); /* PendSV Handler */
void WEAK SysTick_Handler(void); /* SysTick Handler */
/* External interrupt vector handler */
void WEAK WDT_IRQHandler(void); /* Watchdog Timer */
void WEAK TIMER0_IRQHandler(void); /* Timer0 */
void WEAK TIMER1_IRQHandler(void); /* Timer1 */
void WEAK TIMER2_IRQHandler(void); /* Timer2 */
void WEAK TIMER3_IRQHandler(void); /* Timer3 */
void WEAK UART0_IRQHandler(void); /* UART0 */
void WEAK UART1_IRQHandler(void); /* UART1 */
void WEAK UART2_IRQHandler(void); /* UART2 */
void WEAK UART3_IRQHandler(void); /* UART3 */
void WEAK PWM1_IRQHandler(void); /* PWM1 */
void WEAK I2C0_IRQHandler(void); /* I2C0 */
void WEAK I2C1_IRQHandler(void); /* I2C1 */
void WEAK I2C2_IRQHandler(void); /* I2C2 */
void WEAK SPI_IRQHandler(void); /* SPI */
void WEAK SSP0_IRQHandler(void); /* SSP0 */
void WEAK SSP1_IRQHandler(void); /* SSP1 */
void WEAK PLL0_IRQHandler(void); /* PLL0 (Main PLL) */
void WEAK RTC_IRQHandler(void); /* Real Time Clock */
void WEAK EINT0_IRQHandler(void); /* External Interrupt 0 */
void WEAK EINT1_IRQHandler(void); /* External Interrupt 1 */
void WEAK EINT2_IRQHandler(void); /* External Interrupt 2 */
void WEAK EINT3_IRQHandler(void); /* External Interrupt 3 */
void WEAK ADC_IRQHandler(void); /* A/D Converter */
void WEAK BOD_IRQHandler(void); /* Brown Out Detect */
void WEAK USB_IRQHandler(void); /* USB */
void WEAK CAN_IRQHandler(void); /* CAN */
void WEAK DMA_IRQHandler(void); /* GP DMA */
void WEAK I2S_IRQHandler(void); /* I2S */
void WEAK ENET_IRQHandler(void); /* Ethernet */
void WEAK RIT_IRQHandler(void); /* Repetitive Interrupt Timer */
void WEAK MCPWM_IRQHandler(void); /* Motor Control PWM */
void WEAK QEI_IRQHandler(void); /* Quadrature Encoder Interface */
void WEAK PLL1_IRQHandler(void); /* PLL1 (USB PLL) */
/* Exported types --------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
extern unsigned long _etext;
extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */
extern unsigned long _sdata; /* start address for the .data section. defined in linker script */
extern unsigned long _edata; /* end address for the .data section. defined in linker script */
extern unsigned long _sifastcode; /* start address for the initialization values of the .fastcode section. defined in linker script */
extern unsigned long _sfastcode; /* start address for the .fastcode section. defined in linker script */
extern unsigned long _efastcode; /* end address for the .fastcode section. defined in linker script */
extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */
extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */
extern void _estack; /* init value for the stack pointer. defined in linker script */
/* Private typedef -----------------------------------------------------------*/
/* function prototypes ------------------------------------------------------*/
void Reset_Handler(void) __attribute__((__interrupt__));
extern int main(void);
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
#define STACK_SIZE 0x00000200
__attribute__ ((section(".stackarea")))
/* static */ unsigned long pulStack[STACK_SIZE];
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) =
{
/* &_estack, // The initial stack pointer */
(void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), // The initial stack pointer
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
HardFault_Handler, /* Hard Fault Handler */
MemManage_Handler, /* MPU Fault Handler */
BusFault_Handler, /* Bus Fault Handler */
UsageFault_Handler, /* Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* SVCall Handler */
DebugMon_Handler, /* Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* PendSV Handler */
SysTick_Handler, /* SysTick Handler */
// External Interrupts
WDT_IRQHandler, /* Watchdog Timer */
TIMER0_IRQHandler, /* Timer0 */
TIMER1_IRQHandler, /* Timer1 */
TIMER2_IRQHandler, /* Timer2 */
TIMER3_IRQHandler, /* Timer3 */
UART0_IRQHandler, /* UART0 */
UART1_IRQHandler, /* UART1 */
UART2_IRQHandler, /* UART2 */
UART3_IRQHandler, /* UART3 */
PWM1_IRQHandler, /* PWM1 */
I2C0_IRQHandler, /* I2C0 */
I2C1_IRQHandler, /* I2C1 */
I2C2_IRQHandler, /* I2C2 */
SPI_IRQHandler, /* SPI */
SSP0_IRQHandler, /* SSP0 */
SSP1_IRQHandler, /* SSP1 */
PLL0_IRQHandler, /* PLL0 (Main PLL) */
RTC_IRQHandler, /* Real Time Clock */
EINT0_IRQHandler, /* External Interrupt 0 */
EINT1_IRQHandler, /* External Interrupt 1 */
EINT2_IRQHandler, /* External Interrupt 2 */
EINT3_IRQHandler, /* External Interrupt 3 */
ADC_IRQHandler, /* A/D Converter */
BOD_IRQHandler, /* Brown Out Detect */
USB_IRQHandler, /* USB */
CAN_IRQHandler, /* CAN */
DMA_IRQHandler, /* GP DMA */
I2S_IRQHandler, /* I2S */
ENET_IRQHandler, /* Ethernet */
RIT_IRQHandler, /* Repetitive Interrupt Timer */
MCPWM_IRQHandler, /* Motor Control PWM */
QEI_IRQHandler, /* Quadrature Encoder Interface */
PLL1_IRQHandler, /* PLL1 (USB PLL) */
};
/*******************************************************************************
* Function Name : Reset_Handler
* Description : This is the code that gets called when the processor first starts execution
* following a reset event. Only the absolutely necessary set is performed,
* after which the application supplied main() routine is called.
* Input :
* Output :
* Return :
*******************************************************************************/
void Reset_Handler(void)
{
SystemInit();
unsigned long *pulDest;
unsigned long *pulSrc;
//
// Copy the data segment initializers from flash to SRAM in ROM mode
//
if (&_sidata != &_sdata) { // only if needed
pulSrc = &_sidata;
for(pulDest = &_sdata; pulDest < &_edata; ) {
*(pulDest++) = *(pulSrc++);
}
}
// Copy the .fastcode code from ROM to SRAM
if (&_sifastcode != &_sfastcode) { // only if needed
pulSrc = &_sifastcode;
for(pulDest = &_sfastcode; pulDest < &_efastcode; ) {
*(pulDest++) = *(pulSrc++);
}
}
//
// Zero fill the bss segment.
//
for(pulDest = &_sbss; pulDest < &_ebss; )
{
*(pulDest++) = 0;
}
//
// Call the application's entry point.
//
main();
}
//*****************************************************************************
//
// Provide weak aliases for each Exception handler to the Default_Handler.
// As they are weak aliases, any function with the same name will override
// this definition.
//
//*****************************************************************************
#pragma weak MemManage_Handler = Default_Handler /* MPU Fault Handler */
#pragma weak BusFault_Handler = Default_Handler /* Bus Fault Handler */
#pragma weak UsageFault_Handler = Default_Handler /* Usage Fault Handler */
#pragma weak SVC_Handler = Default_Handler /* SVCall Handler */
#pragma weak DebugMon_Handler = Default_Handler /* Debug Monitor Handler */
#pragma weak PendSV_Handler = Default_Handler /* PendSV Handler */
#pragma weak SysTick_Handler = Default_Handler /* SysTick Handler */
/* External interrupt vector handler */
#pragma weak WDT_IRQHandler = Default_Handler /* Watchdog Timer */
#pragma weak TIMER0_IRQHandler = Default_Handler /* Timer0 */
#pragma weak TIMER1_IRQHandler = Default_Handler /* Timer1 */
#pragma weak TIMER2_IRQHandler = Default_Handler /* Timer2 */
#pragma weak TIMER3_IRQHandler = Default_Handler /* Timer3 */
#pragma weak UART0_IRQHandler = Default_Handler /* UART0 */
#pragma weak UART1_IRQHandler = Default_Handler /* UART1 */
#pragma weak UART2_IRQHandler = Default_Handler /* UART2 */
#pragma weak UART3_IRQHandler = Default_Handler /* UART3 */
#pragma weak PWM1_IRQHandler = Default_Handler /* PWM1 */
#pragma weak I2C0_IRQHandler = Default_Handler /* I2C0 */
#pragma weak I2C1_IRQHandler = Default_Handler /* I2C1 */
#pragma weak I2C2_IRQHandler = Default_Handler /* I2C2 */
#pragma weak SPI_IRQHandler = Default_Handler /* SPI */
#pragma weak SSP0_IRQHandler = Default_Handler /* SSP0 */
#pragma weak SSP1_IRQHandler = Default_Handler /* SSP1 */
#pragma weak PLL0_IRQHandler = Default_Handler /* PLL0 (Main PLL) */
#pragma weak RTC_IRQHandler = Default_Handler /* Real Time Clock */
#pragma weak EINT0_IRQHandler = Default_Handler /* External Interrupt 0 */
#pragma weak EINT1_IRQHandler = Default_Handler /* External Interrupt 1 */
#pragma weak EINT2_IRQHandler = Default_Handler /* External Interrupt 2 */
#pragma weak EINT3_IRQHandler = Default_Handler /* External Interrupt 3 */
#pragma weak ADC_IRQHandler = Default_Handler /* A/D Converter */
#pragma weak BOD_IRQHandler = Default_Handler /* Brown Out Detect */
#pragma weak USB_IRQHandler = Default_Handler /* USB */
#pragma weak CAN_IRQHandler = Default_Handler /* CAN */
#pragma weak DMA_IRQHandler = Default_Handler /* GP DMA */
#pragma weak I2S_IRQHandler = Default_Handler /* I2S */
#pragma weak ENET_IRQHandler = Default_Handler /* Ethernet */
#pragma weak RIT_IRQHandler = Default_Handler /* Repetitive Interrupt Timer */
#pragma weak MCPWM_IRQHandler = Default_Handler /* Motor Control PWM */
#pragma weak QEI_IRQHandler = Default_Handler /* Quadrature Encoder Interface */
#pragma weak PLL1_IRQHandler = Default_Handler /* PLL1 (USB PLL) */
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
void Default_Handler(void) {
// Go into an infinite loop.
//
while (1) {
}
}

539
lpc17xx/system_LPC17xx.c Normal file
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/**************************************************************************//**
* @file system_LPC17xx.c
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
* for the NXP LPC17xx Device Series
* @version V1.03
* @date 07. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "LPC17xx.h"
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
// <h> System Controls and Status Register (SCS)
// <o1.4> OSCRANGE: Main Oscillator Range Select
// <0=> 1 MHz to 20 MHz
// <1=> 15 MHz to 24 MHz
// <e1.5> OSCEN: Main Oscillator Enable
// </e>
// </h>
//
// <h> Clock Source Select Register (CLKSRCSEL)
// <o2.0..1> CLKSRC: PLL Clock Source Selection
// <0=> Internal RC oscillator
// <1=> Main oscillator
// <2=> RTC oscillator
// </h>
//
// <e3> PLL0 Configuration (Main PLL)
// <h> PLL0 Configuration Register (PLL0CFG)
// <i> F_cco0 = (2 * M * F_in) / N
// <i> F_in must be in the range of 32 kHz to 50 MHz
// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
// <o4.0..14> MSEL: PLL Multiplier Selection
// <6-32768><#-1>
// <i> M Value
// <o4.16..23> NSEL: PLL Divider Selection
// <1-256><#-1>
// <i> N Value
// </h>
// </e>
//
// <e5> PLL1 Configuration (USB PLL)
// <h> PLL1 Configuration Register (PLL1CFG)
// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
// <i> F_cco1 = F_osc * M * 2 * P
// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
// <o6.0..4> MSEL: PLL Multiplier Selection
// <1-32><#-1>
// <i> M Value (for USB maximum value is 4)
// <o6.5..6> PSEL: PLL Divider Selection
// <0=> 1
// <1=> 2
// <2=> 4
// <3=> 8
// <i> P Value
// </h>
// </e>
//
// <h> CPU Clock Configuration Register (CCLKCFG)
// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
// <3-256><#-1>
// </h>
//
// <h> USB Clock Configuration Register (USBCLKCFG)
// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
// <0-15>
// <i> Divide is USBSEL + 1
// </h>
//
// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 6
// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 6
// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 6
// </h>
//
// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
// <0=> Pclk = Cclk / 4
// <1=> Pclk = Cclk
// <2=> Pclk = Cclk / 2
// <3=> Pclk = Hclk / 8
// </h>
//
// <h> Power Control for Peripherals Register (PCONP)
// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
// <o11.3> PCUART0: UART 0 power/clock enable
// <o11.4> PCUART1: UART 1 power/clock enable
// <o11.6> PCPWM1: PWM 1 power/clock enable
// <o11.7> PCI2C0: I2C interface 0 power/clock enable
// <o11.8> PCSPI: SPI interface power/clock enable
// <o11.9> PCRTC: RTC power/clock enable
// <o11.10> PCSSP1: SSP interface 1 power/clock enable
// <o11.12> PCAD: A/D converter power/clock enable
// <o11.13> PCCAN1: CAN controller 1 power/clock enable
// <o11.14> PCCAN2: CAN controller 2 power/clock enable
// <o11.15> PCGPIO: GPIOs power/clock enable
// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
// <o11.17> PCMC: Motor control PWM power/clock enable
// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
// <o11.19> PCI2C1: I2C interface 1 power/clock enable
// <o11.21> PCSSP0: SSP interface 0 power/clock enable
// <o11.22> PCTIM2: Timer 2 power/clock enable
// <o11.23> PCTIM3: Timer 3 power/clock enable
// <o11.24> PCUART2: UART 2 power/clock enable
// <o11.25> PCUART3: UART 3 power/clock enable
// <o11.26> PCI2C2: I2C interface 2 power/clock enable
// <o11.27> PCI2S: I2S interface power/clock enable
// <o11.29> PCGPDMA: GP DMA function power/clock enable
// <o11.30> PCENET: Ethernet block power/clock enable
// <o11.31> PCUSB: USB interface power/clock enable
// </h>
//
// <h> Clock Output Configuration Register (CLKOUTCFG)
// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
// <0=> CPU clock
// <1=> Main oscillator
// <2=> Internal RC oscillator
// <3=> USB clock
// <4=> RTC oscillator
// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
// <1-16><#-1>
// <o12.8> CLKOUT_EN: CLKOUT enable control
// </h>
//
// </e>
*/
#define CLOCK_SETUP 1
#define SCS_Val 0x00000020
#define CLKSRCSEL_Val 0x00000001
#define PLL0_SETUP 1
#define PLL0CFG_Val 0x00050063
#define PLL1_SETUP 1
#define PLL1CFG_Val 0x00000023
#define CCLKCFG_Val 0x00000003
#define USBCLKCFG_Val 0x00000000
#define PCLKSEL0_Val 0x00000000
#define PCLKSEL1_Val 0x00000000
#define PCONP_Val 0x042887DE
#define CLKOUTCFG_Val 0x00000000
/*--------------------- Flash Accelerator Configuration ----------------------
//
// <e> Flash Accelerator Configuration
// <o1.0..1> FETCHCFG: Fetch Configuration
// <0=> Instruction fetches from flash are not buffered
// <1=> One buffer is used for all instruction fetch buffering
// <2=> All buffers may be used for instruction fetch buffering
// <3=> Reserved (do not use this setting)
// <o1.2..3> DATACFG: Data Configuration
// <0=> Data accesses from flash are not buffered
// <1=> One buffer is used for all data access buffering
// <2=> All buffers may be used for data access buffering
// <3=> Reserved (do not use this setting)
// <o1.4> ACCEL: Acceleration Enable
// <o1.5> PREFEN: Prefetch Enable
// <o1.6> PREFOVR: Prefetch Override
// <o1.12..15> FLASHTIM: Flash Access Time
// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
// <5=> 6 CPU clocks (for any CPU clock)
// </e>
*/
#define FLASH_SETUP 1
#define FLASHCFG_Val 0x0000303A
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SCS_Val), ~0x00000030))
#error "SCS: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
#error "CLKSRCSEL: Value out of range!"
#endif
#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
#error "PLL0CFG: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
#error "PLL1CFG: Invalid values of reserved bits!"
#endif
#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
#error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
#endif
#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
#error "USBCLKCFG: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
#error "PCLKSEL0: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
#error "PCLKSEL1: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCONP_Val), 0x10100821))
#error "PCONP: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
#error "CLKOUTCFG: Invalid values of reserved bits!"
#endif
/* Flash Accelerator Configuration -------------------------------------------*/
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
#error "FLASHCFG: Invalid values of reserved bits!"
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (12000000UL) /* Oscillator frequency */
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
/* F_cco0 = (2 * M * F_in) / N */
#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
/* Determine core clock frequency according to settings */
#if (PLL0_SETUP)
#if ((CLKSRCSEL_Val & 0x03) == 1)
#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
#elif ((CLKSRCSEL_Val & 0x03) == 2)
#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
#else
#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
#endif
#else
#if ((CLKSRCSEL_Val & 0x03) == 1)
#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
#elif ((CLKSRCSEL_Val & 0x03) == 2)
#define __CORE_CLK (RTC_CLK / __CCLK_DIV)
#else
#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
#endif
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* Determine clock frequency according to clock register values */
if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
switch (LPC_SC->CLKSRCSEL & 0x03) {
case 0: /* Int. RC oscillator => PLL0 */
case 3: /* Reserved, default to Int. RC */
SystemCoreClock = (IRC_OSC *
((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
break;
case 1: /* Main oscillator => PLL0 */
SystemCoreClock = (OSC_CLK *
((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
break;
case 2: /* RTC oscillator => PLL0 */
SystemCoreClock = (RTC_CLK *
((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
((LPC_SC->CCLKCFG & 0xFF)+ 1));
break;
}
} else {
switch (LPC_SC->CLKSRCSEL & 0x03) {
case 0: /* Int. RC oscillator => PLL0 */
case 3: /* Reserved, default to Int. RC */
SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
break;
case 1: /* Main oscillator => PLL0 */
SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
break;
case 2: /* RTC oscillator => PLL0 */
SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
break;
}
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if (CLOCK_SETUP) /* Clock Setup */
LPC_SC->SCS = SCS_Val;
if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
}
LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
#if (PLL0_SETUP)
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
LPC_SC->PLL0FEED = 0xAA;
LPC_SC->PLL0FEED = 0x55;
LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
LPC_SC->PLL0FEED = 0xAA;
LPC_SC->PLL0FEED = 0x55;
while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
LPC_SC->PLL0FEED = 0xAA;
LPC_SC->PLL0FEED = 0x55;
while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
#endif
#if (PLL1_SETUP)
LPC_SC->PLL1CFG = PLL1CFG_Val;
LPC_SC->PLL1FEED = 0xAA;
LPC_SC->PLL1FEED = 0x55;
LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
LPC_SC->PLL1FEED = 0xAA;
LPC_SC->PLL1FEED = 0x55;
while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
LPC_SC->PLL1FEED = 0xAA;
LPC_SC->PLL1FEED = 0x55;
while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
#else
LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
#endif
LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
#endif
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
LPC_SC->FLASHCFG = FLASHCFG_Val;
#endif
}

60
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/******************************************************************************
* @file: system_LPC17xx.h
* @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
* for the NXP LPC17xx Device Series
* @version: V1.02
* @date: 27. July 2009
*----------------------------------------------------------------------------
*
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC17xx_H
#define __SYSTEM_LPC17xx_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC17xx_H */