grbl-LPC-CoreXY/sim/avr/wdt.h

#define WDTCSR wdt
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE  3
#define WDCE 4
#define WDP3 5
#define WDIE 6
#define WDIF 7

uint16_t wdt;
Bug fixes for timers, added some wdt support for limit debounce. - Typo in timer def, - Handle 8 bit timers correctly, - Don't skip TOP count in CTC mode - added SREG for atomic bit operations 2014-07-10 19:01:03 +02:00			`#define WDTCSR wdt`
			`#define WDP0 0`
			`#define WDP1 1`
			`#define WDP2 2`
			`#define WDE 3`
			`#define WDCE 4`
			`#define WDP3 5`
			`#define WDIE 6`
			`#define WDIF 7`

Total rework of simulator for dev branch. Create separate thread for interrupt processes. Tick-accurate simulation of timers. Non-blocking character input for running in realtime mode. Decouple hardware sim from grbl code as much as possible. Expanded command line options. Provisions for cross-platform solution. 2014-07-04 17:14:54 +02:00			`uint16_t wdt;`