448 lines
11 KiB
C
Executable File
448 lines
11 KiB
C
Executable File
/*
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* Copyright (C) 2016 Stefan Brüns <stefan.bruens@rwth-aachen.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Set the following three defines to your needs */
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#ifndef SDK_PWM_PERIOD_COMPAT_MODE
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#define SDK_PWM_PERIOD_COMPAT_MODE 0
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#endif
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#ifndef PWM_MAX_CHANNELS
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#define PWM_MAX_CHANNELS 8
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#endif
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#define PWM_DEBUG 0
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#define PWM_USE_NMI 1
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/* no user servicable parts beyond this point */
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#define PWM_MAX_TICKS 0x7fffff
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#if SDK_PWM_PERIOD_COMPAT_MODE
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#define PWM_PERIOD_TO_TICKS(x) (x * 0.2)
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#define PWM_DUTY_TO_TICKS(x) (x * 5)
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#define PWM_MAX_DUTY (PWM_MAX_TICKS * 0.2)
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#define PWM_MAX_PERIOD (PWM_MAX_TICKS * 5)
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#else
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#define PWM_PERIOD_TO_TICKS(x) (x)
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#define PWM_DUTY_TO_TICKS(x) (x)
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#define PWM_MAX_DUTY PWM_MAX_TICKS
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#define PWM_MAX_PERIOD PWM_MAX_TICKS
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#endif
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#include <c_types.h>
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#include <pwm.h>
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#include <eagle_soc.h>
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#include <ets_sys.h>
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// from SDK hw_timer.c
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#define TIMER1_DIVIDE_BY_16 0x0004
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#define TIMER1_ENABLE_TIMER 0x0080
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struct pwm_phase {
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uint32_t ticks; ///< delay until next phase, in 200ns units
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uint16_t on_mask; ///< GPIO mask to switch on
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uint16_t off_mask; ///< GPIO mask to switch off
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};
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/* Three sets of PWM phases, the active one, the one used
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* starting with the next cycle, and the one updated
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* by pwm_start. After the update pwm_next_set
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* is set to the last updated set. pwm_current_set is set to
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* pwm_next_set from the interrupt routine during the first
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* pwm phase
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*/
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typedef struct pwm_phase (pwm_phase_array)[PWM_MAX_CHANNELS + 2];
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static pwm_phase_array pwm_phases[3];
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static struct {
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struct pwm_phase* next_set;
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struct pwm_phase* current_set;
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uint8_t current_phase;
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} pwm_state;
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static uint32_t pwm_period;
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static uint32_t pwm_period_ticks;
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static uint32_t pwm_duty[PWM_MAX_CHANNELS];
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static uint16_t gpio_mask[PWM_MAX_CHANNELS];
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static uint8_t pwm_channels;
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// 3-tuples of MUX_REGISTER, MUX_VALUE and GPIO number
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typedef uint32_t (pin_info_type)[3];
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struct gpio_regs {
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uint32_t out; /* 0x60000300 */
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uint32_t out_w1ts; /* 0x60000304 */
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uint32_t out_w1tc; /* 0x60000308 */
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uint32_t enable; /* 0x6000030C */
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uint32_t enable_w1ts; /* 0x60000310 */
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uint32_t enable_w1tc; /* 0x60000314 */
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uint32_t in; /* 0x60000318 */
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uint32_t status; /* 0x6000031C */
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uint32_t status_w1ts; /* 0x60000320 */
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uint32_t status_w1tc; /* 0x60000324 */
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};
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static struct gpio_regs* gpio = (struct gpio_regs*)(0x60000300);
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struct timer_regs {
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uint32_t frc1_load; /* 0x60000600 */
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uint32_t frc1_count; /* 0x60000604 */
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uint32_t frc1_ctrl; /* 0x60000608 */
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uint32_t frc1_int; /* 0x6000060C */
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uint8_t pad[16];
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uint32_t frc2_load; /* 0x60000620 */
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uint32_t frc2_count; /* 0x60000624 */
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uint32_t frc2_ctrl; /* 0x60000628 */
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uint32_t frc2_int; /* 0x6000062C */
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uint32_t frc2_alarm; /* 0x60000630 */
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};
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static struct timer_regs* timer = (struct timer_regs*)(0x60000600);
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static void ICACHE_RAM_ATTR
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pwm_intr_handler(void)
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{
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if ((pwm_state.current_set[pwm_state.current_phase].off_mask == 0) &&
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(pwm_state.current_set[pwm_state.current_phase].on_mask == 0)) {
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pwm_state.current_set = pwm_state.next_set;
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pwm_state.current_phase = 0;
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}
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do {
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// force write to GPIO registers on each loop
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asm volatile ("" : : : "memory");
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gpio->out_w1ts = (uint32_t)(pwm_state.current_set[pwm_state.current_phase].on_mask);
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gpio->out_w1tc = (uint32_t)(pwm_state.current_set[pwm_state.current_phase].off_mask);
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uint32_t ticks = pwm_state.current_set[pwm_state.current_phase].ticks;
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pwm_state.current_phase++;
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if (ticks) {
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if (ticks >= 16) {
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// constant interrupt overhead
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ticks -= 9;
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timer->frc1_int &= ~FRC1_INT_CLR_MASK;
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WRITE_PERI_REG(&timer->frc1_load, ticks);
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return;
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}
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ticks *= 4;
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do {
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ticks -= 1;
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// stop compiler from optimizing delay loop to noop
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asm volatile ("" : : : "memory");
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} while (ticks > 0);
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}
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} while (1);
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}
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/**
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* period: initial period (base unit 1us OR 200ns)
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* duty: array of initial duty values, may be NULL, may be freed after pwm_init
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* pwm_channel_num: number of channels to use
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* pin_info_list: array of pin_info
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*/
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void ICACHE_FLASH_ATTR
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pwm_init(uint32_t period, uint32_t *duty, uint32_t pwm_channel_num,
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uint32_t (*pin_info_list)[3])
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{
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int i, j, n;
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pwm_channels = pwm_channel_num;
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if (pwm_channels > PWM_MAX_CHANNELS)
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pwm_channels = PWM_MAX_CHANNELS;
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for (i = 0; i < 3; i++) {
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for (j = 0; j < (PWM_MAX_CHANNELS + 2); j++) {
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pwm_phases[i][j].ticks = 0;
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pwm_phases[i][j].on_mask = 0;
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pwm_phases[i][j].off_mask = 0;
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}
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}
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pwm_state.current_set = pwm_state.next_set = 0;
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pwm_state.current_phase = 0;
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uint32_t all = 0;
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// PIN info: MUX-Register, Mux-Setting, PIN-Nr
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for (n = 0; n < pwm_channels; n++) {
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pin_info_type* pin_info = &pin_info_list[n];
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PIN_FUNC_SELECT((*pin_info)[0], (*pin_info)[1]);
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gpio_mask[n] = 1 << (*pin_info)[2];
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all |= 1 << (*pin_info)[2];
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if (duty)
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pwm_set_duty(duty[n], n);
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}
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GPIO_REG_WRITE(GPIO_OUT_W1TC_ADDRESS, all);
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GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, all);
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pwm_set_period(period);
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#if PWM_USE_NMI
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ETS_FRC_TIMER1_NMI_INTR_ATTACH(pwm_intr_handler);
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#else
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ETS_FRC_TIMER1_INTR_ATTACH(pwm_intr_handler, NULL);
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#endif
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TM1_EDGE_INT_ENABLE();
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timer->frc1_int &= ~FRC1_INT_CLR_MASK;
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timer->frc1_ctrl = 0;
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pwm_start();
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}
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__attribute__ ((noinline))
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static uint8_t ICACHE_FLASH_ATTR
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_pwm_phases_prep(struct pwm_phase* pwm)
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{
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uint8_t n, phases;
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for (n = 0; n < pwm_channels + 2; n++) {
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pwm[n].ticks = 0;
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pwm[n].on_mask = 0;
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pwm[n].off_mask = 0;
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}
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phases = 1;
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for (n = 0; n < pwm_channels; n++) {
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uint32_t ticks = PWM_DUTY_TO_TICKS(pwm_duty[n]);
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if (ticks == 0) {
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pwm[0].off_mask |= gpio_mask[n];
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} else if (ticks >= pwm_period_ticks) {
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pwm[0].on_mask |= gpio_mask[n];
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} else {
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if (ticks < (pwm_period_ticks/2)) {
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pwm[phases].ticks = ticks;
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pwm[0].on_mask |= gpio_mask[n];
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pwm[phases].off_mask = gpio_mask[n];
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} else {
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pwm[phases].ticks = pwm_period_ticks - ticks;
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pwm[phases].on_mask = gpio_mask[n];
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pwm[0].off_mask |= gpio_mask[n];
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}
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phases++;
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}
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}
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pwm[phases].ticks = pwm_period_ticks;
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// bubble sort, lowest to hightest duty
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n = 2;
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while (n < phases) {
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if (pwm[n].ticks < pwm[n - 1].ticks) {
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struct pwm_phase t = pwm[n];
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pwm[n] = pwm[n - 1];
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pwm[n - 1] = t;
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if (n > 2)
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n--;
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} else {
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n++;
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}
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}
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#if PWM_DEBUG
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int t = 0;
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for (t = 0; t <= phases; t++) {
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ets_printf("%d @%d: %04x %04x\n", t, pwm[t].ticks, pwm[t].on_mask, pwm[t].off_mask);
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}
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#endif
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// shift left to align right edge;
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uint8_t l = 0, r = 1;
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while (r <= phases) {
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uint32_t diff = pwm[r].ticks - pwm[l].ticks;
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if (diff && (diff <= 16)) {
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uint16_t mask = pwm[r].on_mask | pwm[r].off_mask;
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pwm[l].off_mask ^= pwm[r].off_mask;
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pwm[l].on_mask ^= pwm[r].on_mask;
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pwm[0].off_mask ^= pwm[r].on_mask;
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pwm[0].on_mask ^= pwm[r].off_mask;
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pwm[r].ticks = pwm_period_ticks - diff;
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pwm[r].on_mask ^= mask;
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pwm[r].off_mask ^= mask;
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} else {
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l = r;
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}
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r++;
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}
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#if PWM_DEBUG
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for (t = 0; t <= phases; t++) {
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ets_printf("%d @%d: %04x %04x\n", t, pwm[t].ticks, pwm[t].on_mask, pwm[t].off_mask);
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}
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#endif
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// sort again
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n = 2;
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while (n <= phases) {
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if (pwm[n].ticks < pwm[n - 1].ticks) {
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struct pwm_phase t = pwm[n];
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pwm[n] = pwm[n - 1];
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pwm[n - 1] = t;
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if (n > 2)
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n--;
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} else {
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n++;
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}
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}
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// merge same duty
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l = 0, r = 1;
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while (r <= phases) {
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if (pwm[r].ticks == pwm[l].ticks) {
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pwm[l].off_mask |= pwm[r].off_mask;
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pwm[l].on_mask |= pwm[r].on_mask;
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pwm[r].on_mask = 0;
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pwm[r].off_mask = 0;
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} else {
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l++;
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if (l != r) {
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struct pwm_phase t = pwm[l];
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pwm[l] = pwm[r];
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pwm[r] = t;
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}
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}
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r++;
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}
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phases = l;
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#if PWM_DEBUG
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for (t = 0; t <= phases; t++) {
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ets_printf("%d @%d: %04x %04x\n", t, pwm[t].ticks, pwm[t].on_mask, pwm[t].off_mask);
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}
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#endif
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// transform absolute end time to phase durations
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for (n = 0; n < phases; n++) {
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pwm[n].ticks =
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pwm[n + 1].ticks - pwm[n].ticks;
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// subtract common overhead
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pwm[n].ticks--;
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}
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pwm[phases].ticks = 0;
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// do a cyclic shift if last phase is short
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if (pwm[phases - 1].ticks < 16) {
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for (n = 0; n < phases - 1; n++) {
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struct pwm_phase t = pwm[n];
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pwm[n] = pwm[n + 1];
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pwm[n + 1] = t;
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}
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}
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#if PWM_DEBUG
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for (t = 0; t <= phases; t++) {
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ets_printf("%d +%d: %04x %04x\n", t, pwm[t].ticks, pwm[t].on_mask, pwm[t].off_mask);
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}
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ets_printf("\n");
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#endif
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return phases;
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}
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void ICACHE_FLASH_ATTR
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pwm_start(void)
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{
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pwm_phase_array* pwm = &pwm_phases[0];
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if ((*pwm == pwm_state.next_set) ||
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(*pwm == pwm_state.current_set))
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pwm++;
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if ((*pwm == pwm_state.next_set) ||
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(*pwm == pwm_state.current_set))
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pwm++;
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uint8_t phases = _pwm_phases_prep(*pwm);
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// all with 0% / 100% duty - stop timer
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if (phases == 1) {
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if (pwm_state.next_set) {
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#if PWM_DEBUG
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ets_printf("PWM stop\n");
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#endif
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timer->frc1_ctrl = 0;
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ETS_FRC1_INTR_DISABLE();
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}
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pwm_state.next_set = NULL;
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GPIO_REG_WRITE(GPIO_OUT_W1TS_ADDRESS, (*pwm)[0].on_mask);
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GPIO_REG_WRITE(GPIO_OUT_W1TC_ADDRESS, (*pwm)[0].off_mask);
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return;
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}
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// start if not running
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if (!pwm_state.next_set) {
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#if PWM_DEBUG
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ets_printf("PWM start\n");
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#endif
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pwm_state.current_set = pwm_state.next_set = *pwm;
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pwm_state.current_phase = phases - 1;
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ETS_FRC1_INTR_ENABLE();
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RTC_REG_WRITE(FRC1_LOAD_ADDRESS, 0);
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timer->frc1_ctrl = TIMER1_DIVIDE_BY_16 | TIMER1_ENABLE_TIMER;
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return;
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}
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pwm_state.next_set = *pwm;
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}
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void ICACHE_FLASH_ATTR
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pwm_set_duty(uint32_t duty, uint8_t channel)
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{
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if (channel > PWM_MAX_CHANNELS)
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return;
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if (duty > PWM_MAX_DUTY)
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duty = PWM_MAX_DUTY;
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pwm_duty[channel] = duty;
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}
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uint32_t ICACHE_FLASH_ATTR
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pwm_get_duty(uint8_t channel)
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{
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if (channel > PWM_MAX_CHANNELS)
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return 0;
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return pwm_duty[channel];
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}
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void ICACHE_FLASH_ATTR
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pwm_set_period(uint32_t period)
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{
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pwm_period = period;
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if (pwm_period > PWM_MAX_PERIOD)
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pwm_period = PWM_MAX_PERIOD;
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pwm_period_ticks = PWM_PERIOD_TO_TICKS(period);
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}
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uint32_t ICACHE_FLASH_ATTR
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pwm_get_period(void)
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{
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return pwm_period;
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}
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uint32_t ICACHE_FLASH_ATTR
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get_pwm_version(void)
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{
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return 1;
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}
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void ICACHE_FLASH_ATTR
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set_pwm_debug_en(uint8_t print_en)
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{
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(void) print_en;
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}
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