initial commit, running config

EFI/OC/ACPI/SSDT-AWAC.dsl

@@ -0,0 +1,27 @@
+/*
+ * Fix 300-series RTC Bug
+ * For 300-series only. If you can't force enable Legacy RTC in BIOS GUI.
+ * macOS does yet not support AWAC, so we have to force enable RTC. Do not use RTC ACPI patch.
+ * 
+ * The Time and Alarm device provides an alternative to the real time clock (RTC), which is defined as a fixed feature hardware device.
+ * The wake timers allow the system to transition from the S3 (or optionally S4/S5) state to S0 state after a time period elapses.
+ * In comparison with the Real Time Clock (RTC) Alarm, the Time and Alarm device provides a larger scale of flexibility in the operation of the wake timers,
+ * and allows the implementation of the time source to be abstracted from the OSPM.
+ */
+
+DefinitionBlock ("", "SSDT", 2, "ACDT", "AWAC", 0x00000000)
+{
+    External (STAS, IntObj)
+
+    Scope (_SB)
+    {
+        Method (_INI, 0, NotSerialized)  // _INI: Initialize
+        {
+            If (_OSI ("Darwin"))
+            {
+                STAS = One
+            }
+        }
+    }
+}
+

EFI/OC/ACPI/SSDT-EC.dsl

@@ -0,0 +1,69 @@
+/*
+ * AppleUsbPower compatibility table for legacy hardware.
+ *
+ * Be warned that power supply values can be different
+ * for different systems. Depending on the configuration
+ * the values must be present in injected IOKitPersonalities
+ * for com.apple.driver.AppleUSBMergeNub. iPad remains being
+ * the most reliable device for testing USB port charging.
+ *
+ * Try NOT to rename EC0, H_EC, etc. to EC.
+ * These devices are incompatible with macOS and may break
+ * at any time. AppleACPIEC kext must NOT load.
+ * See the disable code below.
+ *
+ * Reference USB: https://applelife.ru/posts/550233
+ * Reference EC: https://applelife.ru/posts/807985
+ */
+DefinitionBlock ("", "SSDT", 2, "ACDT", "SsdtEC", 0x00001000)
+{
+    External (_SB_.PCI0.LPCB, DeviceObj)
+
+    /*
+     * Uncomment replacing EC0 with your own value in case your
+     * motherboard has an existing embedded controller of PNP0C09 type.
+     *
+     * While renaming EC0 to EC might potentially work initially,
+     * it connects an incompatible driver (AppleACPIEC) to your hardware.
+     * This can make your system unbootable at any time or hide bugs that
+     * could trigger randomly.
+     */
+
+    /**
+    External (_SB_.PCI0.LPCB.EC0, DeviceObj)
+
+    Scope (\_SB.PCI0.LPCB.EC0)
+    {
+        Method (_STA, 0, NotSerialized)  // _STA: Status
+        {
+            If (_OSI ("Darwin"))
+            {
+                Return (0)
+            }
+            Else
+            {
+                Return (0x0F)
+            }
+        }
+    }
+    **/
+
+    Scope (\_SB.PCI0.LPCB)
+    {
+        Device (EC)
+        {
+            Name (_HID, "ACID0001")  // _HID: Hardware ID
+            Method (_STA, 0, NotSerialized)  // _STA: Status
+            {
+                If (_OSI ("Darwin"))
+                {
+                    Return (0x0F)
+                }
+                Else
+                {
+                    Return (Zero)
+                }
+            }
+        }
+    }
+}

EFI/OC/ACPI/SSDT-HACK-MSI.dsl

@@ -0,0 +1,85 @@
+DefinitionBlock("", "SSDT", 2, "hack", "HACK-MSI", 0x00000000)
+{
+    External(\_SB.PCI0, DeviceObj) // Ausaetzliches Geraete
+
+        Scope(\_SB.PCI0)
+    {
+
+        Device(THRC) // Zusaetzliches Geraet Thermal subsystem
+        {
+            Name(_ADR, 0x00120000) // _ADR: Address
+                Name(THRC, One) Method(_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+            {
+                If(!Arg2)
+                {
+                    Return(Buffer(){ 0x03 })
+                }
+                Return(Package(){
+                    "built-in", Buffer(){ 0x00 }, 
+                    "device_type", , Buffer(){ "Thermal-Controller" },
+                    "model", Buffer(){ "Cannon Lake PCH Thermal Controller" }, "name",
+                    Buffer(){ "Cannon Lake PCH Thermal Controller" }, "AAPL,slot-name",
+                    Buffer(){ "Internal@0,18,0" }, "compatible", Buffer(){ "pci8086,9d21" },
+                })
+            }
+        }
+
+        Device(XEON) // Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th/8th Gen Core Processor Gaussian Mixture Model
+        {
+            Name(_ADR, 0x00080000) // _ADR: Address
+                Name(XEON, One) Method(_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+            {
+                If(!Arg2)
+                {
+                    Return(Buffer(){ 0x03 })
+                }
+                Return(Package(){
+                    "built-in", Buffer(){ 0x00 },
+                    "device_type", , Buffer(){ "System peripheral" },
+                    "model", Buffer(){ "Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th/8th Gen Core Processor Gaussian Mixture Model" },
+                    "AAPL,slot-name", Buffer(){ "Internal@0,8,0" },
+			        "compatible", Buffer(){ "pci8086,9d21" },
+                })
+            }
+        }
+
+        Device(SPI_) // Cannon Lake PCH SPI Controller
+        {
+            Name(_ADR, 0x001F0005) // _ADR: Address
+                Name(SPI_, One) Method(_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+            {
+                If(!Arg2)
+                {
+                    Return(Buffer(){ 0x03 })
+                }
+                Return(Package(){
+                    "built-in", Buffer(){ 0x00 },
+                    "device_type", , Buffer(){ "Serial bus controller" },
+                    "model", Buffer(){ "Cannon Lake PCH SPI Controller" },
+                    "AAPL,slot-name", Buffer(){ "Internal@0,31,5" },
+			        "compatible", Buffer(){ "pci8086,9d21" },
+                })
+            }
+        }
+
+        Device(RAM_) // Cannon Lake PCH Shared SRAM
+        {
+            Name(_ADR, 0x00140002) // _ADR: Address
+                Name(RAM_, One) Method(_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+            {
+                If(!Arg2)
+                {
+                    Return(Buffer(){ 0x03 })
+                }
+                Return(Package(){
+                    "built-in", Buffer(){ 0x00 },
+                    "device_type", , Buffer(){ "RAM memory" },
+                    "model", Buffer(){ "Cannon Lake PCH Shared SRAM" },
+                    "AAPL,slot-name", Buffer(){ "Internal@0,20,2" },
+			        "compatible", Buffer(){ "pci8086,9d21" },
+                })
+            }
+        }
+
+    }
+}

EFI/OC/ACPI/SSDT-PLUG.dsl

@@ -0,0 +1,50 @@
+/*
+ * XCPM power management compatibility table.
+ */
+DefinitionBlock ("", "SSDT", 2, "ACDT", "CpuPlug", 0x00003000)
+{
+    External (_SB_.PR00, ProcessorObj)
+
+    Scope (\_SB.PR00)
+    {
+        Method (DTGP, 5, NotSerialized)
+        {
+            If ((Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")))
+            {
+                If ((Arg1 == One))
+                {
+                    If ((Arg2 == Zero))
+                    {
+                        Arg4 = Buffer (One)
+                            {
+                                 0x03                                             // .
+                            }
+                        Return (One)
+                    }
+
+                    If ((Arg2 == One))
+                    {
+                        Return (One)
+                    }
+                }
+            }
+
+            Arg4 = Buffer (One)
+                {
+                     0x00                                             // .
+                }
+            Return (Zero)
+        }
+
+        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
+        {
+            Local0 = Package (0x02)
+                {
+                    "plugin-type", 
+                    One
+                }
+            DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
+            Return (Local0)
+        }
+    }
+}

EFI/OC/ACPI/SSDT-SBUS-MCHC.dsl

@@ -0,0 +1,73 @@
+/*
+ * SMBus compatibility table.
+ */
+DefinitionBlock ("", "SSDT", 2, "ACDT", "MCHCSBUS", 0x00000000)
+{
+    External (_SB_.PCI0, DeviceObj)
+    External (_SB_.PCI0.SBUS.BUS0, DeviceObj)
+
+    Scope (_SB.PCI0)
+    {
+        Device (MCHC)
+        {
+            Name (_ADR, Zero)  // _ADR: Address
+        }
+    }
+
+    Device (_SB.PCI0.SBUS.BUS0)
+    {
+        Name (_CID, "smbus")  // _CID: Compatible ID
+        Name (_ADR, Zero)  // _ADR: Address
+        Device (DVL0)
+        {
+            Name (_ADR, 0x57)  // _ADR: Address
+            Name (_CID, "diagsvault")  // _CID: Compatible ID
+            Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
+            {
+                If (!Arg2)
+                {
+                    Return (Buffer (One)
+                    {
+                         0x57                                             // W
+                    })
+                }
+
+                Return (Package (0x02)
+                {
+                    "address", 
+                    0x57
+                })
+            }
+        }
+    }
+
+    Method (DTGP, 5, NotSerialized)
+    {
+        If ((Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")))
+        {
+            If ((Arg1 == One))
+            {
+                If ((Arg2 == Zero))
+                {
+                    Arg4 = Buffer (One)
+                        {
+                             0x03                                             // .
+                        }
+                    Return (One)
+                }
+
+                If ((Arg2 == One))
+                {
+                    Return (One)
+                }
+            }
+        }
+
+        Arg4 = Buffer (One)
+            {
+                 0x00                                             // .
+            }
+        Return (Zero)
+    }
+}
+

EFI/OC/ACPI/SSDT-SET-STAS.dsl

@@ -0,0 +1,27 @@
+/*
+ * Fix 300-series RTC Bug
+ * For 300-series only. If you can't force enable Legacy RTC in BIOS GUI.
+ * macOS does yet not support AWAC, so we have to force enable RTC. Do not use RTC ACPI patch.
+ * 
+ * The Time and Alarm device provides an alternative to the real time clock (RTC), which is defined as a fixed feature hardware device.
+ * The wake timers allow the system to transition from the S3 (or optionally S4/S5) state to S0 state after a time period elapses.
+ * In comparison with the Real Time Clock (RTC) Alarm, the Time and Alarm device provides a larger scale of flexibility in the operation of the wake timers,
+ * and allows the implementation of the time source to be abstracted from the OSPM.
+ */
+
+DefinitionBlock ("", "SSDT", 2, "ACDT", "AWAC", 0x00000000)
+{
+    External (STAS, IntObj)
+
+    Scope (_SB)
+    {
+        Method (_INI, 0, NotSerialized)  // _INI: Initialize
+        {
+            If (_OSI ("Darwin"))
+            {
+                STAS = One
+            }
+        }
+    }
+}
+

EFI/OC/ACPI/SSDT-XOSI.dsl

@@ -0,0 +1,41 @@
+// Override for host defined _OSI to handle "Darwin"...
+
+#ifndef NO_DEFINITIONBLOCK
+DefinitionBlock("", "SSDT", 2, "hack", "_XOSI", 0)
+{
+#endif
+    // All _OSI calls in DSDT are routed to XOSI...
+    // As written, this XOSI simulates "Windows 2015" (which is Windows 10)
+    // Note: According to ACPI spec, _OSI("Windows") must also return true
+    //  Also, it should return true for all previous versions of Windows.
+    Method(XOSI, 1)
+    {
+        // simulation targets
+        // source: (google 'Microsoft Windows _OSI')
+        //  https://docs.microsoft.com/en-us/windows-hardware/drivers/acpi/winacpi-osi
+        Local0 = Package()
+        {
+            //"Windows",              // generic Windows query
+            //"Windows 2001",         // Windows XP
+            //"Windows 2001 SP2",     // Windows XP SP2
+            //"Windows 2001.1",     // Windows Server 2003
+            //"Windows 2001.1 SP1", // Windows Server 2003 SP1
+            //"Windows 2006",         // Windows Vista
+            //"Windows 2006 SP1",     // Windows Vista SP1
+            //"Windows 2006.1",       // Windows Server 2008
+            //"Windows 2009",         // Windows 7/Windows Server 2008 R2
+            //"Windows 2012",         // Windows 8/Windows Server 2012
+            //"Windows 2013",         // Windows 8.1/Windows Server 2012 R2
+            "Windows 2015",         // Windows 10/Windows Server TP
+            //"Windows 2016",       // Windows 10, version 1607
+            //"Windows 2017",       // Windows 10, version 1703
+            //"Windows 2017.2",     // Windows 10, version 1709
+            //"Windows 2018",       // Windows 10, version 1803
+            //"Windows 2018.2",     // Windows 10, version 1809
+        }
+        Return (Ones != Match(Local0, MEQ, Arg0, MTR, 0, 0))
+    }
+#ifndef NO_DEFINITIONBLOCK
+}
+#endif
+//EOF

EFI/OC/ACPI/origin/DumpLog.txt

@@ -0,0 +1,122 @@
+19:099  5:956  Found UEFI Acpi 2.0 RSDP at 8EA70000
+19:099  0:000  Saving ACPI tables from RSDP 8EA70000 to EFI\CLOVER\ACPI\origin ...
+19:099  0:000   8EA70000: 'RSD PTR ', Rev: 2 (Acpi 2.0 or newer), Len: 36 -> RSDP.aml
+19:206  0:106    (Xsdt: 8EA700A8, Rsdt: 8EA70028)
+19:206  0:000    8EA700A8: 'XSDT', 'A M I', Rev: 1, Len: 204 -> XSDT.aml
+19:293  0:087    8EA70028: 'RSDT', 'A M I', Rev: 1, Len: 120 -> RSDT.aml
+19:396  0:102    Tables in Xsdt: 21
+19:396  0:000    0. 8EAADB88: 'FACP', 'A M I', Rev: 6, Len: 276 -> FACP.aml
+19:486  0:090        (Dsdt: 8EA70208, Facs: 8EB1E080, XDsdt: 8EA70208, XFacs: 0)
+19:486  0:000        8EA70208: 'DSDT', 'A M I', Rev: 2, Len: 252286 -> DSDT.aml
+19:623  0:136        8EB1E080: 'FACS', Ver: 2, Len: 64 -> FACS.aml
+19:708  0:084    1. 8EAADCA0: 'APIC', 'A M I', Rev: 4, Len: 188 -> APIC.aml
+19:803  0:094    2. 8EAADD60: 'FPDT', 'A M I', Rev: 1, Len: 68 -> FPDT.aml
+19:903  0:100    3. 8EAADDA8: 'FIDT', 'A M I', Rev: 1, Len: 156 -> FIDT.aml
+19:985  0:081    4. 8EAADE48: 'MCFG', 'A M I', Rev: 1, Len: 60 -> MCFG.aml
+20:116  0:131    5. 8EAADE88: 'SSDT', 'CpuSsdt', Rev: 2, Len: 7007 -> SSDT-0-CpuSsdt.aml (Found hidden SSDT 9 pcs)
+20:231  0:114        * 8E564098: 'SSDT', 'Cpu0Ist', Rev: 2, Len: 1541  53 53 44 54 05 06 00 00 02 E6 50 6D 52 65 66 00 Internal length = 1541 -> SSDT-x0_0-Cpu0Ist.aml
+20:313  0:081        * 8E556018: 'SSDT', 'ApIst', Rev: 2, Len: 1532  53 53 44 54 FC 05 00 00 02 23 50 6D 52 65 66 00 Internal length = 1532 -> SSDT-x0_1-ApIst.aml
+20:414  0:100        * 8E556698: 'SSDT', 'Cpu0Cst', Rev: 2, Len: 1024  53 53 44 54 00 04 00 00 02 D9 50 6D 52 65 66 00 Internal length = 1024 -> SSDT-x0_2-Cpu0Cst.aml
+20:495  0:081        * 8E561A98: 'SSDT', 'ApCst', Rev: 2, Len: 778  53 53 44 54 0A 03 00 00 02 E9 50 6D 52 65 66 00 Internal length = 778 -> SSDT-x0_3-ApCst.aml
+20:616  0:121        * 8E564898: 'SSDT', 'Cpu0Hwp', Rev: 2, Len: 329  53 53 44 54 49 01 00 00 02 51 50 6D 52 65 66 00 Internal length = 329 -> SSDT-x0_4-Cpu0Hwp.aml
+20:717  0:100        * 8E554018: 'SSDT', 'ApHwp', Rev: 2, Len: 791  53 53 44 54 17 03 00 00 02 E3 50 6D 52 65 66 00 Internal length = 791 -> SSDT-x0_5-ApHwp.aml
+20:818  0:100        * 8E561018: 'SSDT', 'HwpLvt', Rev: 2, Len: 1828  53 53 44 54 24 07 00 00 02 CA 50 6D 52 65 66 00 Internal length = 1828 -> SSDT-x0_6-HwpLvt.aml
+20:926  0:108        * 8E564718: 'SSDT', 'Cpu0Psd', Rev: 2, Len: 244  53 53 44 54 F4 00 00 00 02 37 50 6D 52 65 66 00 Internal length = 244 -> SSDT-x0_7-Cpu0Psd.aml
+21:015  0:088        * 8E555018: 'SSDT', 'ApPsd', Rev: 2, Len: 2736  53 53 44 54 B0 0A 00 00 02 AB 50 6D 52 65 66 00 Internal length = 2736 -> SSDT-x0_8-ApPsd.aml
+21:096  0:081  
+21:096  0:000    6. 8EAAF9E8: 'SSDT', 'SaSsdt', Rev: 2, Len: 12742 -> SSDT-1-SaSsdt.aml
+21:197  0:101    7. 8EAB2BB0: 'SSDT', 'PegSsdt', Rev: 2, Len: 9243 -> SSDT-2-PegSsdt.aml
+21:286  0:088    8. 8EAB4FD0: 'HPET', 'A M I', Rev: 1, Len: 56 -> HPET.aml
+21:374  0:087    9. 8EAB5008: 'SSDT', 'Ther_Rvp', Rev: 2, Len: 4014 -> SSDT-3-Ther_Rvp.aml
+21:475  0:101    10. 8EAB5FB8: 'SSDT', 'xh_cfsd4', Rev: 2, Len: 12238 -> SSDT-4-xh_cfsd4.aml
+21:596  0:120    11. 8EAB8F88: 'UEFI', 'A M I', Rev: 1, Len: 66 -> UEFI.aml
+21:697  0:100    12. 8EAB8FD0: 'LPIT', 'A M I', Rev: 1, Len: 148 -> LPIT.aml
+21:825  0:128    13. 8EAB9068: 'SSDT', 'PtidDevc', Rev: 2, Len: 10206 -> SSDT-5-PtidDevc.aml
+21:907  0:081    14. 8EABB848: 'SSDT', 'TbtTypeC', Rev: 2, Len: 5346 -> SSDT-6-TbtTypeC.aml
+22:014  0:107    15. 8EABCD30: 'DBGP', 'A M I', Rev: 1, Len: 52 -> DBGP.aml
+22:103  0:088    16. 8EABCD68: 'DBG2', 'A M I', Rev: 0, Len: 84 -> DBG2.aml
+22:204  0:100    17. 8EABCDC0: 'SSDT', 'UsbCTabl', Rev: 2, Len: 7015 -> SSDT-7-UsbCTabl.aml
+22:292  0:088    18. 8EABE928: 'SSDT', 'ADebTabl', Rev: 2, Len: 324 -> SSDT-8-ADebTabl.aml
+22:374  0:081    19. 8EABEA70: 'BGRT', 'A M I', Rev: 1, Len: 56 -> BGRT.aml
+22:475  0:100    20. 8EABEAA8: 'WSMT', 'A M I', Rev: 1, Len: 40 -> WSMT.aml
+22:569  0:094    Tables in Rsdt: 21
+22:569  0:000    0. 8EA70180: 'FACP', 'A M I', Rev: 2, Len: 132 -> RSDT-FACP.aml
+22:712  0:143        (Dsdt: 8EA70208, Facs: 8EB1E040)
+22:712  0:000        8EA70208: 'DSDT', 'A M I', Rev: 2, Len: 252286
+22:717  0:004        8EB1E040: 'FACS', Ver: 0, Len: 64 -> RSDT-FACS.aml
+22:799  0:081    1. 8EAADCA0: 'APIC', 'A M I', Rev: 4, Len: 188
+22:799  0:000    2. 8EAADD60: 'FPDT', 'A M I', Rev: 1, Len: 68
+22:799  0:000    3. 8EAADDA8: 'FIDT', 'A M I', Rev: 1, Len: 156
+22:799  0:000    4. 8EAADE48: 'MCFG', 'A M I', Rev: 1, Len: 60
+22:799  0:000    5. 8EAADE88: 'SSDT', 'CpuSsdt', Rev: 2, Len: 7007
+22:799  0:000    6. 8EAAF9E8: 'SSDT', 'SaSsdt', Rev: 2, Len: 12742
+22:799  0:000    7. 8EAB2BB0: 'SSDT', 'PegSsdt', Rev: 2, Len: 9243
+22:799  0:000    8. 8EAB4FD0: 'HPET', 'A M I', Rev: 1, Len: 56
+22:799  0:000    9. 8EAB5008: 'SSDT', 'Ther_Rvp', Rev: 2, Len: 4014
+22:799  0:000    10. 8EAB5FB8: 'SSDT', 'xh_cfsd4', Rev: 2, Len: 12238
+22:799  0:000    11. 8EAB8F88: 'UEFI', 'A M I', Rev: 1, Len: 66
+22:799  0:000    12. 8EAB8FD0: 'LPIT', 'A M I', Rev: 1, Len: 148
+22:799  0:000    13. 8EAB9068: 'SSDT', 'PtidDevc', Rev: 2, Len: 10206
+22:799  0:000    14. 8EABB848: 'SSDT', 'TbtTypeC', Rev: 2, Len: 5346
+22:799  0:000    15. 8EABCD30: 'DBGP', 'A M I', Rev: 1, Len: 52
+22:799  0:000    16. 8EABCD68: 'DBG2', 'A M I', Rev: 0, Len: 84
+22:799  0:000    17. 8EABCDC0: 'SSDT', 'UsbCTabl', Rev: 2, Len: 7015
+22:799  0:000    18. 8EABE928: 'SSDT', 'ADebTabl', Rev: 2, Len: 324
+22:799  0:000    19. 8EABEA70: 'BGRT', 'A M I', Rev: 1, Len: 56
+22:799  0:000    20. 8EABEAA8: 'WSMT', 'A M I', Rev: 1, Len: 40
+22:799  0:000  Found UEFI Acpi 1.0 RSDP at 8EA70000
+22:799  0:000  Printing ACPI tables from RSDP 8EA70000 ...
+22:799  0:000   8EA70000: 'RSD PTR ', Rev: 2 (Acpi 2.0 or newer), Len: 36
+22:799  0:000    (Xsdt: 8EA700A8, Rsdt: 8EA70028)
+22:799  0:000    8EA700A8: 'XSDT', 'A M I', Rev: 1, Len: 204
+22:799  0:000    8EA70028: 'RSDT', 'A M I', Rev: 1, Len: 120
+22:799  0:000    Tables in Xsdt: 21
+22:799  0:000    0. 8EAADB88: 'FACP', 'A M I', Rev: 6, Len: 276
+22:799  0:000        (Dsdt: 8EA70208, Facs: 8EB1E080, XDsdt: 8EA70208, XFacs: 0)
+22:799  0:000        8EA70208: 'DSDT', 'A M I', Rev: 2, Len: 252286
+22:804  0:004        8EB1E080: 'FACS', Ver: 2, Len: 64
+22:804  0:000    1. 8EAADCA0: 'APIC', 'A M I', Rev: 4, Len: 188
+22:804  0:000    2. 8EAADD60: 'FPDT', 'A M I', Rev: 1, Len: 68
+22:804  0:000    3. 8EAADDA8: 'FIDT', 'A M I', Rev: 1, Len: 156
+22:804  0:000    4. 8EAADE48: 'MCFG', 'A M I', Rev: 1, Len: 60
+22:804  0:000    5. 8EAADE88: 'SSDT', 'CpuSsdt', Rev: 2, Len: 7007
+22:804  0:000    6. 8EAAF9E8: 'SSDT', 'SaSsdt', Rev: 2, Len: 12742
+22:804  0:000    7. 8EAB2BB0: 'SSDT', 'PegSsdt', Rev: 2, Len: 9243
+22:804  0:000    8. 8EAB4FD0: 'HPET', 'A M I', Rev: 1, Len: 56
+22:804  0:000    9. 8EAB5008: 'SSDT', 'Ther_Rvp', Rev: 2, Len: 4014
+22:804  0:000    10. 8EAB5FB8: 'SSDT', 'xh_cfsd4', Rev: 2, Len: 12238
+22:804  0:000    11. 8EAB8F88: 'UEFI', 'A M I', Rev: 1, Len: 66
+22:804  0:000    12. 8EAB8FD0: 'LPIT', 'A M I', Rev: 1, Len: 148
+22:804  0:000    13. 8EAB9068: 'SSDT', 'PtidDevc', Rev: 2, Len: 10206
+22:804  0:000    14. 8EABB848: 'SSDT', 'TbtTypeC', Rev: 2, Len: 5346
+22:804  0:000    15. 8EABCD30: 'DBGP', 'A M I', Rev: 1, Len: 52
+22:804  0:000    16. 8EABCD68: 'DBG2', 'A M I', Rev: 0, Len: 84
+22:804  0:000    17. 8EABCDC0: 'SSDT', 'UsbCTabl', Rev: 2, Len: 7015
+22:804  0:000    18. 8EABE928: 'SSDT', 'ADebTabl', Rev: 2, Len: 324
+22:804  0:000    19. 8EABEA70: 'BGRT', 'A M I', Rev: 1, Len: 56
+22:804  0:000    20. 8EABEAA8: 'WSMT', 'A M I', Rev: 1, Len: 40
+22:804  0:000    Tables in Rsdt: 21
+22:804  0:000    0. 8EA70180: 'FACP', 'A M I', Rev: 2, Len: 132
+22:804  0:000        (Dsdt: 8EA70208, Facs: 8EB1E040)
+22:804  0:000        8EA70208: 'DSDT', 'A M I', Rev: 2, Len: 252286
+22:809  0:004        8EB1E040: 'FACS', Ver: 0, Len: 64
+22:809  0:000    1. 8EAADCA0: 'APIC', 'A M I', Rev: 4, Len: 188
+22:809  0:000    2. 8EAADD60: 'FPDT', 'A M I', Rev: 1, Len: 68
+22:809  0:000    3. 8EAADDA8: 'FIDT', 'A M I', Rev: 1, Len: 156
+22:809  0:000    4. 8EAADE48: 'MCFG', 'A M I', Rev: 1, Len: 60
+22:809  0:000    5. 8EAADE88: 'SSDT', 'CpuSsdt', Rev: 2, Len: 7007
+22:809  0:000    6. 8EAAF9E8: 'SSDT', 'SaSsdt', Rev: 2, Len: 12742
+22:809  0:000    7. 8EAB2BB0: 'SSDT', 'PegSsdt', Rev: 2, Len: 9243
+22:809  0:000    8. 8EAB4FD0: 'HPET', 'A M I', Rev: 1, Len: 56
+22:809  0:000    9. 8EAB5008: 'SSDT', 'Ther_Rvp', Rev: 2, Len: 4014
+22:809  0:000    10. 8EAB5FB8: 'SSDT', 'xh_cfsd4', Rev: 2, Len: 12238
+22:809  0:000    11. 8EAB8F88: 'UEFI', 'A M I', Rev: 1, Len: 66
+22:809  0:000    12. 8EAB8FD0: 'LPIT', 'A M I', Rev: 1, Len: 148
+22:809  0:000    13. 8EAB9068: 'SSDT', 'PtidDevc', Rev: 2, Len: 10206
+22:809  0:000    14. 8EABB848: 'SSDT', 'TbtTypeC', Rev: 2, Len: 5346
+22:809  0:000    15. 8EABCD30: 'DBGP', 'A M I', Rev: 1, Len: 52
+22:809  0:000    16. 8EABCD68: 'DBG2', 'A M I', Rev: 0, Len: 84
+22:809  0:000    17. 8EABCDC0: 'SSDT', 'UsbCTabl', Rev: 2, Len: 7015
+22:809  0:000    18. 8EABE928: 'SSDT', 'ADebTabl', Rev: 2, Len: 324
+22:809  0:000    19. 8EABEA70: 'BGRT', 'A M I', Rev: 1, Len: 56
+22:809  0:000    20. 8EABEAA8: 'WSMT', 'A M I', Rev: 1, Len: 40

EFI/OC/ACPI/ssdt-i7-9700.dsl

@@ -0,0 +1,247 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140210-00 [Feb 10 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ * 
+ * Original Table Header:
+ *     Signature        "SSDT"
+ *     Length           0x0000036A (874)
+ *     Revision         0x01
+ *     Checksum         0x00
+ *     OEM ID           "APPLE "
+ *     OEM Table ID     "CpuPm"
+ *     OEM Revision     0x00021500 (136448)
+ *     Compiler ID      "INTL"
+ *     Compiler Version 0x20140210 (538182160)
+ */
+
+DefinitionBlock ("ssdt.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00021500)
+{
+    External (\_SB_.PR00, DeviceObj)
+    External (\_SB_.PR01, DeviceObj)
+    External (\_SB_.PR02, DeviceObj)
+    External (\_SB_.PR03, DeviceObj)
+    External (\_SB_.PR04, DeviceObj)
+    External (\_SB_.PR05, DeviceObj)
+    External (\_SB_.PR06, DeviceObj)
+    External (\_SB_.PR07, DeviceObj)
+
+    Scope (\_SB_.PR00)
+    {
+        Method (_INI, 0, NotSerialized)
+        {
+            Store ("ssdtPRGen version.....: 21.5 / Mac OS X 10.15.1 (19B88)", Debug)
+            Store ("custom mode...........: 0", Debug)
+            Store ("host processor........: Intel(R) Core(TM) i7-9700 CPU @ 3.00GHz", Debug)
+            Store ("target processor......: i7-9700", Debug)
+            Store ("number of processors..: 1", Debug)
+            Store ("baseFrequency.........: 800", Debug)
+            Store ("frequency.............: 3000", Debug)
+            Store ("busFrequency..........: 100", Debug)
+            Store ("logicalCPUs...........: 8", Debug)
+            Store ("maximum TDP...........: 65", Debug)
+            Store ("packageLength.........: 40", Debug)
+            Store ("turboStates...........: 17", Debug)
+            Store ("maxTurboFrequency.....: 4700", Debug)
+            Store ("machdep.xcpm.mode.....: 1", Debug)
+        }
+
+        Name (APLF, Zero)
+        Name (APSN, 0x11)
+        Name (APSS, Package (0x28)
+        {
+            /* High Frequency Modes (turbo) */
+            Package (0x06) { 0x125C, 0x00FDE8, 0x0A, 0x0A, 0x2F00, 0x2F00 },
+            Package (0x06) { 0x11F8, 0x00FDE8, 0x0A, 0x0A, 0x2E00, 0x2E00 },
+            Package (0x06) { 0x1194, 0x00FDE8, 0x0A, 0x0A, 0x2D00, 0x2D00 },
+            Package (0x06) { 0x1130, 0x00FDE8, 0x0A, 0x0A, 0x2C00, 0x2C00 },
+            Package (0x06) { 0x10CC, 0x00FDE8, 0x0A, 0x0A, 0x2B00, 0x2B00 },
+            Package (0x06) { 0x1068, 0x00FDE8, 0x0A, 0x0A, 0x2A00, 0x2A00 },
+            Package (0x06) { 0x1004, 0x00FDE8, 0x0A, 0x0A, 0x2900, 0x2900 },
+            Package (0x06) { 0x0FA0, 0x00FDE8, 0x0A, 0x0A, 0x2800, 0x2800 },
+            Package (0x06) { 0x0F3C, 0x00FDE8, 0x0A, 0x0A, 0x2700, 0x2700 },
+            Package (0x06) { 0x0ED8, 0x00FDE8, 0x0A, 0x0A, 0x2600, 0x2600 },
+            Package (0x06) { 0x0E74, 0x00FDE8, 0x0A, 0x0A, 0x2500, 0x2500 },
+            Package (0x06) { 0x0E10, 0x00FDE8, 0x0A, 0x0A, 0x2400, 0x2400 },
+            Package (0x06) { 0x0DAC, 0x00FDE8, 0x0A, 0x0A, 0x2300, 0x2300 },
+            Package (0x06) { 0x0D48, 0x00FDE8, 0x0A, 0x0A, 0x2200, 0x2200 },
+            Package (0x06) { 0x0CE4, 0x00FDE8, 0x0A, 0x0A, 0x2100, 0x2100 },
+            Package (0x06) { 0x0C80, 0x00FDE8, 0x0A, 0x0A, 0x2000, 0x2000 },
+            Package (0x06) { 0x0C1C, 0x00FDE8, 0x0A, 0x0A, 0x1F00, 0x1F00 },
+            /* High Frequency Modes (non-turbo) */
+            Package (0x06) { 0x0BB8, 0x00FDE8, 0x0A, 0x0A, 0x1E00, 0x1E00 },
+            Package (0x06) { 0x0B54, 0x00F2A9, 0x0A, 0x0A, 0x1D00, 0x1D00 },
+            Package (0x06) { 0x0AF0, 0x00E79F, 0x0A, 0x0A, 0x1C00, 0x1C00 },
+            Package (0x06) { 0x0A8C, 0x00DCCA, 0x0A, 0x0A, 0x1B00, 0x1B00 },
+            Package (0x06) { 0x0A28, 0x00D229, 0x0A, 0x0A, 0x1A00, 0x1A00 },
+            Package (0x06) { 0x09C4, 0x00C7BC, 0x0A, 0x0A, 0x1900, 0x1900 },
+            Package (0x06) { 0x0960, 0x00BD82, 0x0A, 0x0A, 0x1800, 0x1800 },
+            Package (0x06) { 0x08FC, 0x00B37B, 0x0A, 0x0A, 0x1700, 0x1700 },
+            Package (0x06) { 0x0898, 0x00A9A7, 0x0A, 0x0A, 0x1600, 0x1600 },
+            Package (0x06) { 0x0834, 0x00A005, 0x0A, 0x0A, 0x1500, 0x1500 },
+            Package (0x06) { 0x07D0, 0x009694, 0x0A, 0x0A, 0x1400, 0x1400 },
+            Package (0x06) { 0x076C, 0x008D55, 0x0A, 0x0A, 0x1300, 0x1300 },
+            Package (0x06) { 0x0708, 0x008447, 0x0A, 0x0A, 0x1200, 0x1200 },
+            Package (0x06) { 0x06A4, 0x007B68, 0x0A, 0x0A, 0x1100, 0x1100 },
+            Package (0x06) { 0x0640, 0x0072BA, 0x0A, 0x0A, 0x1000, 0x1000 },
+            Package (0x06) { 0x05DC, 0x006A3C, 0x0A, 0x0A, 0x0F00, 0x0F00 },
+            Package (0x06) { 0x0578, 0x0061EC, 0x0A, 0x0A, 0x0E00, 0x0E00 },
+            Package (0x06) { 0x0514, 0x0059CC, 0x0A, 0x0A, 0x0D00, 0x0D00 },
+            Package (0x06) { 0x04B0, 0x0051D9, 0x0A, 0x0A, 0x0C00, 0x0C00 },
+            Package (0x06) { 0x044C, 0x004A15, 0x0A, 0x0A, 0x0B00, 0x0B00 },
+            Package (0x06) { 0x03E8, 0x00427E, 0x0A, 0x0A, 0x0A00, 0x0A00 },
+            Package (0x06) { 0x0384, 0x003B14, 0x0A, 0x0A, 0x0900, 0x0900 },
+            /* Low Frequency Mode */
+            Package (0x06) { 0x0320, 0x0033D6, 0x0A, 0x0A, 0x0800, 0x0800 }
+        })
+
+        Method (ACST, 0, NotSerialized)
+        {
+            Store ("Method _SB_.PR00.ACST Called", Debug)
+            Store ("PR00 C-States    : 13", Debug)
+
+            /* Low Power Modes for PR00 */
+            Return (Package (0x05)
+            {
+                One,
+                0x03,
+                Package (0x04)
+                {
+                    ResourceTemplate ()
+                    {
+                        Register (FFixedHW,
+                            0x01,               // Bit Width
+                            0x02,               // Bit Offset
+                            0x0000000000000000, // Address
+                            0x01,               // Access Size
+                            )
+                    },
+                    One,
+                    Zero,
+                    0x03E8
+                },
+
+                Package (0x04)
+                {
+                    ResourceTemplate ()
+                    {
+                        Register (FFixedHW,
+                            0x01,               // Bit Width
+                            0x02,               // Bit Offset
+                            0x0000000000000010, // Address
+                            0x03,               // Access Size
+                            )
+                    },
+                    0x03,
+                    0xCD,
+                    0x01F4
+                },
+
+                Package (0x04)
+                {
+                    ResourceTemplate ()
+                    {
+                        Register (FFixedHW,
+                            0x01,               // Bit Width
+                            0x02,               // Bit Offset
+                            0x0000000000000020, // Address
+                            0x03,               // Access Size
+                            )
+                    },
+                    0x06,
+                    0xF5,
+                    0x015E
+                }
+            })
+        }
+
+        Method (_DSM, 4, NotSerialized)
+        {
+            Store ("Method _SB_.PR00._DSM Called", Debug)
+
+            If (LEqual (Arg2, Zero))
+            {
+                Return (Buffer (One)
+                {
+                    0x03
+                })
+            }
+
+            Return (Package (0x02)
+            {
+                "plugin-type",
+                One
+            })
+        }
+    }
+
+    Scope (\_SB_.PR01)
+    {
+        Method (APSS, 0, NotSerialized)
+        {
+            Store ("Method _SB_.PR01.APSS Called", Debug)
+
+            Return (\_SB_.PR00.APSS)
+        }
+    }
+
+    Scope (\_SB_.PR02)
+    {
+        Method (APSS, 0, NotSerialized)
+        {
+            Store ("Method _SB_.PR02.APSS Called", Debug)
+
+            Return (\_SB_.PR00.APSS)
+        }
+    }
+
+    Scope (\_SB_.PR03)
+    {
+        Method (APSS, 0, NotSerialized)
+        {
+            Store ("Method _SB_.PR03.APSS Called", Debug)
+
+            Return (\_SB_.PR00.APSS)
+        }
+    }
+
+    Scope (\_SB_.PR04)
+    {
+        Method (APSS, 0, NotSerialized)
+        {
+            Store ("Method _SB_.PR04.APSS Called", Debug)
+
+            Return (\_SB_.PR00.APSS)
+        }
+    }
+
+    Scope (\_SB_.PR05)
+    {
+        Method (APSS, 0, NotSerialized)
+        {
+            Store ("Method _SB_.PR05.APSS Called", Debug)
+
+            Return (\_SB_.PR00.APSS)
+        }
+    }
+
+    Scope (\_SB_.PR06)
+    {
+        Method (APSS, 0, NotSerialized)
+        {
+            Store ("Method _SB_.PR06.APSS Called", Debug)
+
+            Return (\_SB_.PR00.APSS)
+        }
+    }
+
+    Scope (\_SB_.PR07)
+    {
+        Method (APSS, 0, NotSerialized)
+        {
+            Store ("Method _SB_.PR07.APSS Called", Debug)
+
+            Return (\_SB_.PR00.APSS)
+        }
+    }
+}